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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
| commit | b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9 (patch) | |
| tree | 67565add4984989a53566cb7836cfadc52f2e39e /test/CodeGen/SystemZ/alloca-01.ll | |
| parent | 3ee0673e4f5f0324ecd0a65507009b0748ed072c (diff) | |
| download | external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.zip external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.gz external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.bz2 | |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/alloca-01.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/alloca-01.ll | 32 |
1 files changed, 8 insertions, 24 deletions
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll index 1852c91..df14e27 100644 --- a/test/CodeGen/SystemZ/alloca-01.ll +++ b/test/CodeGen/SystemZ/alloca-01.ll @@ -1,8 +1,7 @@ ; Test variable-sized allocas and addresses based on them in cases where ; stack arguments are needed. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C @@ -15,34 +14,19 @@ declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g) ; There are two stack arguments, so an offset of 160 + 2 * 8 == 176 ; is added to the copy of %r15. define i64 @f1(i64 %length, i64 %index) { -; The full allocation sequence is: -; -; la %r0, 7(%r2) 1 -; nill %r0, 0xfff8 1 -; lgr %r1, %r15 2 -; sgr %r1, %r0 1 2 -; lgr %r15, %r1 2 -; -; The third instruction does not depend on the first two, so check for -; two fully-ordered sequences. -; ; FIXME: a better sequence would be: ; ; lgr %r1, %r15 ; sgr %r1, %r2 -; nill %r1, 0xfff8 +; risbg %r1, %r1, 0, 188, 0 ; lgr %r15, %r1 ; -; CHECK1: f1: -; CHECK1: la %r0, 7(%r2) -; CHECK1: nill %r0, 65528 -; CHECK1: sgr %r1, %r0 -; CHECK1: lgr %r15, %r1 -; -; CHECK2: f1: -; CHECK2: lgr %r1, %r15 -; CHECK2: sgr %r1, %r0 -; CHECK2: lgr %r15, %r1 +; CHECK: f1: +; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2) +; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0 +; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15 +; CHECK: sgr [[REG3]], [[REG2]] +; CHECK: lgr %r15, [[REG3]] ; ; CHECK-A: f1: ; CHECK-A: lgr %r15, %r1 |