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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
commit | b503b49b5105b6aad7d2a015468b84b0f64dfe8e (patch) | |
tree | a60966043fae51838cb2faa08531a7ed078e4fb6 /test/CodeGen/SystemZ/args-05.ll | |
parent | 1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07 (diff) | |
download | external_llvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.zip external_llvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.tar.gz external_llvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.tar.bz2 |
[SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target.
This version of the patch incorporates feedback from a review by
Sean Silva. Thanks to all reviewers!
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/args-05.ll')
-rw-r--r-- | test/CodeGen/SystemZ/args-05.ll | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/args-05.ll b/test/CodeGen/SystemZ/args-05.ll new file mode 100644 index 0000000..9fa193a --- /dev/null +++ b/test/CodeGen/SystemZ/args-05.ll @@ -0,0 +1,47 @@ +; Test that we take advantage of signext and zeroext annotations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Zero extension of something that is already zero-extended. +define void @f1(i32 zeroext %r2, i64 *%r3) { +; CHECK: f1: +; CHECK-NOT: %r2 +; CHECK: stg %r2, 0(%r3) +; CHECK: br %r14 + %conv = zext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Sign extension of something that is already sign-extended. +define void @f2(i32 signext %r2, i64 *%r3) { +; CHECK: f2: +; CHECK-NOT: %r2 +; CHECK: stg %r2, 0(%r3) +; CHECK: br %r14 + %conv = sext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Sign extension of something that is already zero-extended. +define void @f3(i32 zeroext %r2, i64 *%r3) { +; CHECK: f3: +; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2 +; CHECK: stg [[REGISTER]], 0(%r3) +; CHECK: br %r14 + %conv = sext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Zero extension of something that is already sign-extended. +define void @f4(i32 signext %r2, i64 *%r3) { +; CHECK: f4: +; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2 +; CHECK: stg [[REGISTER]], 0(%r3) +; CHECK: br %r14 + %conv = zext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} |