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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-10-01 13:18:56 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-10-01 13:18:56 +0000
commit645d250b84fe0d097e7813b980ae58daeca2c2e6 (patch)
tree546e722390d56140fee454cc642a0d234d85291c /test/CodeGen/SystemZ/asm-18.ll
parent2e1625475fab156b98204fa73c168ca4a828b775 (diff)
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[SystemZ] Allow integer insertions with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/asm-18.ll')
-rw-r--r--test/CodeGen/SystemZ/asm-18.ll38
1 files changed, 38 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/asm-18.ll b/test/CodeGen/SystemZ/asm-18.ll
index 6126b50..fc71895 100644
--- a/test/CodeGen/SystemZ/asm-18.ll
+++ b/test/CodeGen/SystemZ/asm-18.ll
@@ -315,3 +315,41 @@ define void @f14(i32 %x, i32 %y) {
call void asm sideeffect "blah $0", "r"(i32 %val)
ret void
}
+
+; Test immediate insertion involving high registers.
+define void @f15() {
+; CHECK-LABEL: f15:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: iihh [[REG]], 4660
+; CHECK: stepb [[REG]]
+; CHECK: iihl [[REG]], 34661
+; CHECK: stepc [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=h"()
+ %and1 = and i32 %res1, 65535
+ %or1 = or i32 %and1, 305397760
+ %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %or1)
+ %and2 = and i32 %res2, -65536
+ %or2 = or i32 %and2, 34661
+ call void asm sideeffect "stepc $0", "h"(i32 %or2)
+ ret void
+}
+
+; Test immediate insertion involving low registers.
+define void @f16() {
+; CHECK-LABEL: f16:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: iilh [[REG]], 4660
+; CHECK: stepb [[REG]]
+; CHECK: iill [[REG]], 34661
+; CHECK: stepc [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=r"()
+ %and1 = and i32 %res1, 65535
+ %or1 = or i32 %and1, 305397760
+ %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %or1)
+ %and2 = and i32 %res2, -65536
+ %or2 = or i32 %and2, 34661
+ call void asm sideeffect "stepc $0", "r"(i32 %or2)
+ ret void
+}