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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-31 11:36:35 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-31 11:36:35 +0000 |
| commit | b3f912b510f8040690864126351b7021980558bb (patch) | |
| tree | b767382a270aba304d043390e89558e023b63c6d /test/CodeGen/SystemZ/atomicrmw-sub-02.ll | |
| parent | 8395251c0a1f16531e7f4d11a766a4a1e3d25520 (diff) | |
| download | external_llvm-b3f912b510f8040690864126351b7021980558bb.zip external_llvm-b3f912b510f8040690864126351b7021980558bb.tar.gz external_llvm-b3f912b510f8040690864126351b7021980558bb.tar.bz2 | |
[SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source. I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead. The AND IMMEDIATE form is shorter
and is less likely to be cracked.
This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register. The patch uses the z196 instruction RISBLG for this instead.
This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now. Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/atomicrmw-sub-02.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-sub-02.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll index 499a606..6f8e26e 100644 --- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll @@ -14,14 +14,14 @@ ; instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 -; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) ; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: sr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) ; CHECK: jlh [[LABEL]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 @@ -48,14 +48,14 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We add 0x80000000 to the rotated word. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 -; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) ; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: afi [[ROT]], -2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) ; CHECK: jlh [[LABEL]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 |