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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
| commit | b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9 (patch) | |
| tree | 67565add4984989a53566cb7836cfadc52f2e39e /test/CodeGen/SystemZ/insert-01.ll | |
| parent | 3ee0673e4f5f0324ecd0a65507009b0748ed072c (diff) | |
| download | external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.zip external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.gz external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.bz2 | |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/insert-01.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/insert-01.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll index 98ddf56..2ff9ff4 100644 --- a/test/CodeGen/SystemZ/insert-01.ll +++ b/test/CodeGen/SystemZ/insert-01.ll @@ -33,7 +33,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) { ; register value. We can use IC but must keep the original mask. define i32 @f3(i32 %orig, i8 *%ptr) { ; CHECK: f3: -; CHECK: nill %r2, 65024 +; CHECK: risbg %r2, %r2, 32, 182, 0 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 %val = load i8 *%ptr @@ -46,7 +46,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) { ; Like f3, but with the operands reversed. define i32 @f4(i32 %orig, i8 *%ptr) { ; CHECK: f4: -; CHECK: nill %r2, 65024 +; CHECK: risbg %r2, %r2, 32, 182, 0 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 %val = load i8 *%ptr |