Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 11 insertions, 11 deletions

diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index c3d445a..1c6be7b 100644
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 255
@@ -33,7 +33,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGC with no displacement.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i8 *%src) {
 
 ; Check the high end of the LLGC range.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i64 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLGC range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i8 *%src) {
 
 ; Check the low end of the LLGC range.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i64 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i8 *%src) {
 
 ; Check that LLGC allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGCR.  We want
 ; to use LLGC if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr