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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/SystemZ/int-move-08.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/SystemZ/int-move-08.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/int-move-08.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll index 56fcbc6..d28d298 100644 --- a/test/CodeGen/SystemZ/int-move-08.ll +++ b/test/CodeGen/SystemZ/int-move-08.ll @@ -18,7 +18,7 @@ define i32 @f1() { ; CHECK-LABEL: f1: ; CHECK: lhrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = sext i16 %val to i32 ret i32 %ext } @@ -28,7 +28,7 @@ define i32 @f2() { ; CHECK-LABEL: f2: ; CHECK: llhrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = zext i16 %val to i32 ret i32 %ext } @@ -49,7 +49,7 @@ define void @f4() { ; CHECK: lrl %r0, gsrc32 ; CHECK: strl %r0, gdst32 ; CHECK: br %r14 - %val = load i32 *@gsrc32 + %val = load i32 , i32 *@gsrc32 store i32 %val, i32 *@gdst32 ret void } @@ -60,7 +60,7 @@ define i32 @f5() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u ; CHECK: lh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = sext i16 %val to i32 ret i32 %ext } @@ -71,7 +71,7 @@ define i32 @f6() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u ; CHECK: llh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = zext i16 %val to i32 ret i32 %ext } @@ -95,7 +95,7 @@ define void @f8() { ; CHECK: larl [[REG:%r[0-5]]], gdst32u ; CHECK: st [[VAL]], 0([[REG]]) ; CHECK: br %r14 - %val = load i32 *@gsrc32u, align 2 + %val = load i32 , i32 *@gsrc32u, align 2 store i32 %val, i32 *@gdst32u, align 2 ret void } @@ -109,9 +109,9 @@ define void @f9() { ; CHECK: srl [[VAL]], 1 ; CHECK: stc [[VAL]], 1([[REG]]) ; CHECK: br %r14 - %ptr1 = getelementptr [2 x i8] *@garray8, i64 0, i64 0 - %ptr2 = getelementptr [2 x i8] *@garray8, i64 0, i64 1 - %val = load i8 *%ptr1 + %ptr1 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 0 + %ptr2 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 1 + %val = load i8 , i8 *%ptr1 %shr = lshr i8 %val, 1 store i8 %shr, i8 *%ptr2 ret void @@ -125,9 +125,9 @@ define void @f10() { ; CHECK: srl [[VAL]], 1 ; CHECK: sthrl [[VAL]], garray16+2 ; CHECK: br %r14 - %ptr1 = getelementptr [2 x i16] *@garray16, i64 0, i64 0 - %ptr2 = getelementptr [2 x i16] *@garray16, i64 0, i64 1 - %val = load i16 *%ptr1 + %ptr1 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 0 + %ptr2 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 1 + %val = load i16 , i16 *%ptr1 %shr = lshr i16 %val, 1 store i16 %shr, i16 *%ptr2 ret void |