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authorPirama Arumuga Nainar <pirama@google.com>2015-04-10 22:08:18 +0000
committerAndroid Git Automerger <android-git-automerger@android.com>2015-04-10 22:08:18 +0000
commit13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch)
tree1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/SystemZ/int-mul-01.ll
parent0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff)
parent31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff)
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am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949': Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/SystemZ/int-mul-01.ll')
-rw-r--r--test/CodeGen/SystemZ/int-mul-01.ll34
1 files changed, 17 insertions, 17 deletions
diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll
index d5f7155..b0adc18 100644
--- a/test/CodeGen/SystemZ/int-mul-01.ll
+++ b/test/CodeGen/SystemZ/int-mul-01.ll
@@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f1:
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
- %half = load i16 *%src
+ %half = load i16 , i16 *%src
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: mh %r2, 4094(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 2047
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 2047
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f3:
; CHECK: mhy %r2, 4096(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 2048
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 2048
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f4:
; CHECK: mhy %r2, 524286(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 262143
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 262143
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) {
; CHECK: agfi %r3, 524288
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 262144
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 262144
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f6:
; CHECK: mhy %r2, -2(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 -1
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 -1
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) {
; CHECK-LABEL: f7:
; CHECK: mhy %r2, -524288(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 -262144
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 -262144
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) {
; CHECK: agfi %r3, -524290
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
- %ptr = getelementptr i16 *%src, i64 -262145
- %half = load i16 *%ptr
+ %ptr = getelementptr i16, i16 *%src, i64 -262145
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4094
%ptr = inttoptr i64 %add2 to i16 *
- %half = load i16 *%ptr
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res
@@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4096
%ptr = inttoptr i64 %add2 to i16 *
- %half = load i16 *%ptr
+ %half = load i16 , i16 *%ptr
%rhs = sext i16 %half to i32
%res = mul i32 %lhs, %rhs
ret i32 %res