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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:08:44 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:08:44 +0000 |
| commit | 1ff62e182e648c72e6fce4f9d7911f2edfd914d2 (patch) | |
| tree | 713f6f25e06617b6df62022247d59ecf0b2392b5 /test/CodeGen/SystemZ | |
| parent | 8819c84aed10777ba91d4e862229882b8da0b272 (diff) | |
| download | external_llvm-1ff62e182e648c72e6fce4f9d7911f2edfd914d2.zip external_llvm-1ff62e182e648c72e6fce4f9d7911f2edfd914d2.tar.gz external_llvm-1ff62e182e648c72e6fce4f9d7911f2edfd914d2.tar.bz2 | |
[SystemZ] Allow integer XOR involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
| -rw-r--r-- | test/CodeGen/SystemZ/asm-18.ll | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/asm-18.ll b/test/CodeGen/SystemZ/asm-18.ll index 4d0547f..bec8dee 100644 --- a/test/CodeGen/SystemZ/asm-18.ll +++ b/test/CodeGen/SystemZ/asm-18.ll @@ -395,3 +395,45 @@ define void @f18() { call void asm sideeffect "stepd $0", "r"(i32 %or3) ret void } + +; Test immediate XOR involving high registers. +define void @f19() { +; CHECK-LABEL: f19: +; CHECK: stepa [[REG:%r[0-5]]] +; CHECK: xihf [[REG]], 305397760 +; CHECK: stepb [[REG]] +; CHECK: xihf [[REG]], 34661 +; CHECK: stepc [[REG]] +; CHECK: xihf [[REG]], 12345678 +; CHECK: stepd [[REG]] +; CHECK: br %r14 + %res1 = call i32 asm "stepa $0", "=h"() + %xor1 = xor i32 %res1, 305397760 + %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %xor1) + %xor2 = xor i32 %res2, 34661 + %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %xor2) + %xor3 = xor i32 %res3, 12345678 + call void asm sideeffect "stepd $0", "h"(i32 %xor3) + ret void +} + +; Test immediate XOR involving low registers. +define void @f20() { +; CHECK-LABEL: f20: +; CHECK: stepa [[REG:%r[0-5]]] +; CHECK: xilf [[REG]], 305397760 +; CHECK: stepb [[REG]] +; CHECK: xilf [[REG]], 34661 +; CHECK: stepc [[REG]] +; CHECK: xilf [[REG]], 12345678 +; CHECK: stepd [[REG]] +; CHECK: br %r14 + %res1 = call i32 asm "stepa $0", "=r"() + %xor1 = xor i32 %res1, 305397760 + %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %xor1) + %xor2 = xor i32 %res2, 34661 + %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %xor2) + %xor3 = xor i32 %res3, 12345678 + call void asm sideeffect "stepd $0", "r"(i32 %xor3) + ret void +} |