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| author | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:45:17 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:45:17 +0000 |
| commit | 8239daf7c83a65a189c352cce3191cdc3bbfe151 (patch) | |
| tree | 84b82c2cf503208d1f67007255f2f56fdb383c55 /test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | |
| parent | 41957f6eb2271e5f1981b32a873d1b58217c6411 (diff) | |
| download | external_llvm-8239daf7c83a65a189c352cce3191cdc3bbfe151.zip external_llvm-8239daf7c83a65a189c352cce3191cdc3bbfe151.tar.gz external_llvm-8239daf7c83a65a189c352cce3191cdc3bbfe151.tar.bz2 | |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll index 080341c..9ed6a01 100644 --- a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll +++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll @@ -23,8 +23,6 @@ entry: %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] ; Constant pool load followed by add. ; Then clobber the loaded register, not the sum. -; CHECK: vldr.64 -; CHECK: vadd.f64 ; CHECK: vldr.64 [[LDR:d.*]], ; CHECK: LPC0_0: ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] |