diff options
author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-18 22:29:44 +0000 |
---|---|---|
committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-18 22:29:44 +0000 |
commit | 0465bcffbbffb5ff5f420787b4350cb8abb196f7 (patch) | |
tree | 0a93caba63fa7bd50f0ab959cd83a4d84e9cb85a /test/CodeGen/Thumb2 | |
parent | 6a5e2832d0a30719602f9befe61f35ab19299de7 (diff) | |
download | external_llvm-0465bcffbbffb5ff5f420787b4350cb8abb196f7.zip external_llvm-0465bcffbbffb5ff5f420787b4350cb8abb196f7.tar.gz external_llvm-0465bcffbbffb5ff5f420787b4350cb8abb196f7.tar.bz2 |
TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.
Fix it in LiveVariableAnalysis by adding the <undef> flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106333 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2')
-rw-r--r-- | test/CodeGen/Thumb2/crash.ll | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb2/crash.ll b/test/CodeGen/Thumb2/crash.ll index 19b1d25..87af9d1 100644 --- a/test/CodeGen/Thumb2/crash.ll +++ b/test/CodeGen/Thumb2/crash.ll @@ -19,3 +19,31 @@ entry: } declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind + +@sbuf = common global [16 x i32] zeroinitializer, align 16 ; <[16 x i32]*> [#uses=5] +@dbuf = common global [16 x i32] zeroinitializer ; <[16 x i32]*> [#uses=2] + +; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger. +; The first INSERT_SUBREG needs an <undef> use operand for that to work. +define arm_apcscc i32 @main() nounwind { +bb.nph: + br label %bb + +bb: ; preds = %bb, %bb.nph + %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ] ; <i32> [#uses=4] + %scevgep = getelementptr [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1] + %scevgep5 = getelementptr [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1] + store i32 %0, i32* %scevgep, align 4 + store i32 -1, i32* %scevgep5, align 4 + %1 = add nsw i32 %0, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %1, 16 ; <i1> [#uses=1] + br i1 %exitcond, label %bb2, label %bb + +bb2: ; preds = %bb + %2 = load <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %3 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %4 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %5 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5) nounwind + ret i32 0 +} |