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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-05 20:30:20 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-05 20:30:20 +0000 |
| commit | 740cd657f3d9d4e88614831c70a649f9257164da (patch) | |
| tree | 55acdd0c3c13cc20ea4e1b1863f80b4cc62f21f8 /test/CodeGen/Thumb2 | |
| parent | 036ebfd87434bc30a0e51f4b9a3d55ab49ee5509 (diff) | |
| download | external_llvm-740cd657f3d9d4e88614831c70a649f9257164da.zip external_llvm-740cd657f3d9d4e88614831c70a649f9257164da.tar.gz external_llvm-740cd657f3d9d4e88614831c70a649f9257164da.tar.bz2 | |
Don't break the IV update in TLI::SimplifySetCC().
LSR always tries to make the ICmp in the loop latch use the incremented
induction variable. This allows the induction variable to be kept in a
single register.
When the induction variable limit is equal to the stride,
SimplifySetCC() would break LSR's hard work by transforming:
(icmp (add iv, stride), stride) --> (cmp iv, 0)
This forced us to use lea for the IC update, preventing the simpler
incl+cmp.
<rdar://problem/7643606>
<rdar://problem/11184260>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2')
| -rw-r--r-- | test/CodeGen/Thumb2/lsr-deficiency.ll | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll index 9ff114e..9aaa821 100644 --- a/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -3,11 +3,6 @@ ; This now reduces to a single induction variable. -; TODO: It still gets a GPR shuffle at the end of the loop -; This is because something in instruction selection has decided -; that comparing the pre-incremented value with zero is better -; than comparing the post-incremented value with -4. - @G = external global i32 ; <i32*> [#uses=2] @array = external global i32* ; <i32**> [#uses=1] @@ -20,9 +15,9 @@ entry: bb: ; preds = %bb, %entry ; CHECK: LBB0_1: -; CHECK: cmp [[R2:r[0-9]+]], #0 -; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1 -; CHECK: mov [[R2]], [[REGISTER]] +; CHECK: subs [[R2:r[0-9]+]], #1 +; CHECK: cmp.w [[R2]], #-1 +; CHECK: bne LBB0_1 %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] |