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authorJim Grosbach <grosbach@apple.com>2013-03-02 20:16:24 +0000
committerJim Grosbach <grosbach@apple.com>2013-03-02 20:16:24 +0000
commit7bf504c58fcf1345f0278d6dab3840a45a623965 (patch)
treebeff2d2d6efbc06f03671dd19a0348745e24f993 /test/CodeGen/Thumb2
parent65da9f1ce14800c137fcd8c32f3ad12c9bebd9bf (diff)
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ARM: Creating a vector from a lane of another.
The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2')
-rw-r--r--test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll14
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll b/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll
new file mode 100644
index 0000000..937ecc0
--- /dev/null
+++ b/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
+
+define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
+; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128]
+; CHECK: add.w r[[ADDR:[0-9]+]], r[[SOURCE]], {{r[0-9]+}}, lsl #2
+; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[ADDR]]:32]
+; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
+ %val = extractelement <4 x i32> %phitmp, i32 %lane
+ %r1 = insertelement <4 x i32> undef, i32 %val, i32 1
+ %r2 = insertelement <4 x i32> %r1, i32 %val, i32 2
+ %r3 = insertelement <4 x i32> %r2, i32 %val, i32 3
+ store <4 x i32> %r3, <4 x i32>* %p, align 4
+ ret void
+}