- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the

  memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 17 insertions, 0 deletions

diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll
new file mode 100644
index 0000000..44a3f46
--- /dev/null
+++ b/test/CodeGen/Thumb/barrier.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=thumb -mattr=+v6  | FileCheck %s
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
+
+define void @t1() {
+; CHECK: t1:
+; CHECK: blx {{_*}}sync_synchronize
+  call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
+  ret void
+}
+
+define void @t2() {
+; CHECK: t2:
+; CHECK: blx {{_*}}sync_synchronize
+  call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
+  ret void
+}