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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-28 00:31:43 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-28 00:31:43 +0000 |
| commit | 5e1d21856de4bf387cccf8365885c45c87642dfb (patch) | |
| tree | 078ca6cfb36d36bb5d7a922edbb705bdb52b3e76 /test/CodeGen/Thumb | |
| parent | 66f3f9e7356761c91f8063a38b37293ce750c1c2 (diff) | |
| download | external_llvm-5e1d21856de4bf387cccf8365885c45c87642dfb.zip external_llvm-5e1d21856de4bf387cccf8365885c45c87642dfb.tar.gz external_llvm-5e1d21856de4bf387cccf8365885c45c87642dfb.tar.bz2 | |
v4, v5 does not support sxtb / sxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb')
| -rw-r--r-- | test/CodeGen/Thumb/ldr_ext.ll | 58 |
1 files changed, 40 insertions, 18 deletions
diff --git a/test/CodeGen/Thumb/ldr_ext.ll b/test/CodeGen/Thumb/ldr_ext.ll index f8b9d15..73b97f2 100644 --- a/test/CodeGen/Thumb/ldr_ext.ll +++ b/test/CodeGen/Thumb/ldr_ext.ll @@ -1,34 +1,56 @@ -; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s +; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s -check-prefix=V5 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6 -define i32 @test1(i8* %v.pntr.s0.u1) { -; CHECK: test1: -; CHECK: ldrb - %tmp.u = load i8* %v.pntr.s0.u1 +; rdar://7176514 + +define i32 @test1(i8* %t1) nounwind { +; V5: ldrb + +; V6: ldrb + %tmp.u = load i8* %t1 %tmp1.s = zext i8 %tmp.u to i32 ret i32 %tmp1.s } -define i32 @test2(i16* %v.pntr.s0.u1) { -; CHECK: test2: -; CHECK: ldrh - %tmp.u = load i16* %v.pntr.s0.u1 +define i32 @test2(i16* %t1) nounwind { +; V5: ldrh + +; V6: ldrh + %tmp.u = load i16* %t1 %tmp1.s = zext i16 %tmp.u to i32 ret i32 %tmp1.s } -define i32 @test3(i8* %v.pntr.s1.u0) { -; CHECK: test3: -; CHECK: ldrb -; CHECK: sxtb - %tmp.s = load i8* %v.pntr.s1.u0 +define i32 @test3(i8* %t0) nounwind { +; V5: ldrb +; V5: lsls +; V5: asrs + +; V6: ldrb +; V6: sxtb + %tmp.s = load i8* %t0 %tmp1.s = sext i8 %tmp.s to i32 ret i32 %tmp1.s } -define i32 @test4() { -; CHECK: test4: -; CHECK: movs -; CHECK: ldrsh +define i32 @test4(i16* %t0) nounwind { +; V5: ldrh +; V5: lsls +; V5: asrs + +; V6: ldrh +; V6: sxth + %tmp.s = load i16* %t0 + %tmp1.s = sext i16 %tmp.s to i32 + ret i32 %tmp1.s +} + +define i32 @test5() nounwind { +; V5: movs r0, #0 +; V5: ldrsh + +; V6: movs r0, #0 +; V6: ldrsh %tmp.s = load i16* null %tmp1.s = sext i16 %tmp.s to i32 ret i32 %tmp1.s |