Do not share a single unknown val# for all the live ranges merged into a physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70026 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 19 insertions, 0 deletions

diff --git a/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
new file mode 100644
index 0000000..981d327
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 2
+; rdar://6806252
+
+define i64 @test(i32* %tmp13) nounwind {
+entry:
+	br label %while.cond
+
+while.cond:		; preds = %while.cond, %entry
+	%tmp15 = load i32* %tmp13		; <i32> [#uses=2]
+	%bf.lo = lshr i32 %tmp15, 1		; <i32> [#uses=1]
+	%bf.lo.cleared = and i32 %bf.lo, 2147483647		; <i32> [#uses=1]
+	%conv = zext i32 %bf.lo.cleared to i64		; <i64> [#uses=1]
+	%bf.lo.cleared25 = and i32 %tmp15, 1		; <i32> [#uses=1]
+	%tobool = icmp ne i32 %bf.lo.cleared25, 0		; <i1> [#uses=1]
+	br i1 %tobool, label %while.cond, label %while.end
+
+while.end:		; preds = %while.cond
+	ret i64 %conv
+}