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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-07-14 21:30:27 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-07-14 21:30:27 +0000 |
| commit | b7e230d999deec5c90ee51a7c2bbc6ee5be0a914 (patch) | |
| tree | c0505b116ffc3e1e9cc850dddd28b7cdab114bc6 /test/CodeGen/X86/2012-07-10-shufnorm.ll | |
| parent | 27982e110817e373ed85064eb844bbaec0fe6771 (diff) | |
| download | external_llvm-b7e230d999deec5c90ee51a7c2bbc6ee5be0a914.zip external_llvm-b7e230d999deec5c90ee51a7c2bbc6ee5be0a914.tar.gz external_llvm-b7e230d999deec5c90ee51a7c2bbc6ee5be0a914.tar.bz2 | |
Add a dagcombine optimization to convert concat_vectors of undefs into a single undef.
The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/2012-07-10-shufnorm.ll')
| -rw-r--r-- | test/CodeGen/X86/2012-07-10-shufnorm.ll | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/CodeGen/X86/2012-07-10-shufnorm.ll b/test/CodeGen/X86/2012-07-10-shufnorm.ll new file mode 100644 index 0000000..e39df58 --- /dev/null +++ b/test/CodeGen/X86/2012-07-10-shufnorm.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx | FileCheck %s + +; CHECK: ocl +define void @ocl() { +entry: + %vext = shufflevector <2 x double> zeroinitializer, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit = shufflevector <8 x double> %vext, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit1 = insertelement <8 x double> %vecinit, double undef, i32 2 + %vecinit3 = insertelement <8 x double> %vecinit1, double undef, i32 3 + %vecinit5 = insertelement <8 x double> %vecinit3, double 0.000000e+00, i32 4 + %vecinit9 = shufflevector <8 x double> %vecinit5, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 9, i32 10> + store <8 x double> %vecinit9, <8 x double>* undef + ret void +; CHECK: vxorps +; CHECK: ret +} + |