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author | Preston Gurd <preston.gurd@intel.com> | 2013-03-04 18:13:57 +0000 |
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committer | Preston Gurd <preston.gurd@intel.com> | 2013-03-04 18:13:57 +0000 |
commit | 9a2cfffdb6340c54ff553c1b81364d0f17fa8f45 (patch) | |
tree | 999ad911d34f3f83d1140500e731228c5f07df84 /test/CodeGen/X86/atom-bypass-slow-division-64.ll | |
parent | ff4faabd2d98776372f45f7592482c9239cc40f2 (diff) | |
download | external_llvm-9a2cfffdb6340c54ff553c1b81364d0f17fa8f45.zip external_llvm-9a2cfffdb6340c54ff553c1b81364d0f17fa8f45.tar.gz external_llvm-9a2cfffdb6340c54ff553c1b81364d0f17fa8f45.tar.bz2 |
Bypass Slow Divides
* Only apply divide bypass optimization when not optimizing for size.
* Fixed bug caused by constant for 0 value of type Int32,
used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/atom-bypass-slow-division-64.ll')
-rw-r--r-- | test/CodeGen/X86/atom-bypass-slow-division-64.ll | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/test/CodeGen/X86/atom-bypass-slow-division-64.ll b/test/CodeGen/X86/atom-bypass-slow-division-64.ll new file mode 100644 index 0000000..a3bbea3 --- /dev/null +++ b/test/CodeGen/X86/atom-bypass-slow-division-64.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux -march=x86-64 | FileCheck %s + +; Additional tests for 64-bit divide bypass + +define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_quotient: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: ret +; CHECK: divw +; CHECK: ret + %result = sdiv i64 %a, %b + ret i64 %result +} + +define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_remainder: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: ret +; CHECK: divw +; CHECK: ret + %result = srem i64 %a, %b + ret i64 %result +} + +define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_quotient_and_remainder: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: divw +; CHECK: addq +; CHECK: ret +; CHECK-NOT: idivq +; CHECK-NOT: divw + %resultdiv = sdiv i64 %a, %b + %resultrem = srem i64 %a, %b + %result = add i64 %resultdiv, %resultrem + ret i64 %result +} |