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| author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
| commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
| tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/X86/bitcast-mmx.ll | |
| parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
| download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 | |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/X86/bitcast-mmx.ll')
| -rw-r--r-- | test/CodeGen/X86/bitcast-mmx.ll | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/test/CodeGen/X86/bitcast-mmx.ll b/test/CodeGen/X86/bitcast-mmx.ll new file mode 100644 index 0000000..de1cb5a --- /dev/null +++ b/test/CodeGen/X86/bitcast-mmx.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s + +define i32 @t0(i64 %x) { +; CHECK-LABEL: t0: +; CHECK: # BB#0:{{.*}} %entry +; CHECK: movd %[[REG1:[a-z]+]], %mm0 +; CHECK-NEXT: pshufw $238, %mm0, %mm0 +; CHECK-NEXT: movd %mm0, %eax +; CHECK-NEXT: retq +entry: + %0 = bitcast i64 %x to <4 x i16> + %1 = bitcast <4 x i16> %0 to x86_mmx + %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18) + %3 = bitcast x86_mmx %2 to <4 x i16> + %4 = bitcast <4 x i16> %3 to <1 x i64> + %5 = extractelement <1 x i64> %4, i32 0 + %6 = bitcast i64 %5 to <2 x i32> + %7 = extractelement <2 x i32> %6, i32 0 + ret i32 %7 +} + +define i64 @t1(i64 %x, i32 %n) { +; CHECK-LABEL: t1: +; CHECK: # BB#0:{{.*}} %entry +; CHECK: movd %[[REG2:[a-z]+]], %mm0 +; CHECK-NEXT: movd %[[REG1]], %mm1 +; CHECK-NEXT: psllq %mm0, %mm1 +; CHECK-NEXT: movd %mm1, %rax +; CHECK-NEXT: retq +entry: + %0 = bitcast i64 %x to x86_mmx + %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n) + %2 = bitcast x86_mmx %1 to i64 + ret i64 %2 +} + +define i64 @t2(i64 %x, i32 %n, i32 %w) { +; CHECK-LABEL: t2: +; CHECK: # BB#0:{{.*}} %entry +; CHECK: movd %[[REG4:[a-z]+]], %mm0 +; CHECK-NEXT: movd %[[REG6:[a-z0-9]+]], %mm1 +; CHECK-NEXT: psllq %mm0, %mm1 +; CHECK-NEXT: movd %[[REG1]], %mm0 +; CHECK-NEXT: por %mm1, %mm0 +; CHECK-NEXT: movd %mm0, %rax +; CHECK-NEXT: retq +entry: + %0 = insertelement <2 x i32> undef, i32 %w, i32 0 + %1 = insertelement <2 x i32> %0, i32 0, i32 1 + %2 = bitcast <2 x i32> %1 to x86_mmx + %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n) + %4 = bitcast i64 %x to x86_mmx + %5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3) + %6 = bitcast x86_mmx %5 to i64 + ret i64 %6 +} + +define i64 @t3(<1 x i64>* %y, i32* %n) { +; CHECK-LABEL: t3: +; CHECK: # BB#0:{{.*}} %entry +; CHECK: movq (%[[REG1]]), %mm0 +; CHECK-NEXT: psllq (%[[REG3:[a-z]+]]), %mm0 +; CHECK-NEXT: movd %mm0, %rax +; CHECK-NEXT: retq +entry: + %0 = bitcast <1 x i64>* %y to x86_mmx* + %1 = load x86_mmx* %0, align 8 + %2 = load i32* %n, align 4 + %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2) + %4 = bitcast x86_mmx %3 to i64 + ret i64 %4 +} + +declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) +declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) +declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) + |