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| author | Dan Gohman <gohman@apple.com> | 2009-06-04 22:49:04 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-06-04 22:49:04 +0000 |
| commit | ae3a0be92e33bc716722aa600983fc1535acb122 (patch) | |
| tree | 768333097a76cc105813c7c636daf6259e6a0fc7 /test/CodeGen/X86/extract-combine.ll | |
| parent | d18e31ae17390d9c6f6cf93d18badf962452031d (diff) | |
| download | external_llvm-ae3a0be92e33bc716722aa600983fc1535acb122.zip external_llvm-ae3a0be92e33bc716722aa600983fc1535acb122.tar.gz external_llvm-ae3a0be92e33bc716722aa600983fc1535acb122.tar.bz2 | |
Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/extract-combine.ll')
| -rw-r--r-- | test/CodeGen/X86/extract-combine.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/X86/extract-combine.ll b/test/CodeGen/X86/extract-combine.ll index 9172dce..842ec24 100644 --- a/test/CodeGen/X86/extract-combine.ll +++ b/test/CodeGen/X86/extract-combine.ll @@ -7,9 +7,9 @@ entry: %tmp518 = shufflevector <16 x float> %tmp74.i25762, <16 x float> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; <<4 x float>> [#uses=1] %movss.i25611 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp518, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] %conv3.i25615 = shufflevector <4 x float> %movss.i25611, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] - %sub.i25620 = sub <4 x float> %conv3.i25615, zeroinitializer ; <<4 x float>> [#uses=1] - %mul.i25621 = mul <4 x float> zeroinitializer, %sub.i25620 ; <<4 x float>> [#uses=1] - %add.i25622 = add <4 x float> zeroinitializer, %mul.i25621 ; <<4 x float>> [#uses=1] + %sub.i25620 = fsub <4 x float> %conv3.i25615, zeroinitializer ; <<4 x float>> [#uses=1] + %mul.i25621 = fmul <4 x float> zeroinitializer, %sub.i25620 ; <<4 x float>> [#uses=1] + %add.i25622 = fadd <4 x float> zeroinitializer, %mul.i25621 ; <<4 x float>> [#uses=1] store <4 x float> %add.i25622, <4 x float>* null unreachable } |