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authorEvan Cheng <evan.cheng@apple.com>2011-01-06 07:58:36 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-01-06 07:58:36 +0000
commit461f1fc359dff438dad25e809499845b10a3d032 (patch)
tree143a2a682ffdd84409d6bd1673e22630d42d565e /test/CodeGen/X86/memset-2.ll
parentcce240d26bbf1c2bec9cfff4838d8d807b215586 (diff)
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Use movups to lower memcpy and memset even if it's not fast (like corei7).
The theory is it's still faster than a pair of movq / a quad of movl. This will probably hurt older chips like P4 but should run faster on current and future Intel processors. rdar://8817010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/memset-2.ll')
-rw-r--r--test/CodeGen/X86/memset-2.ll16
1 files changed, 15 insertions, 1 deletions
diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll
index ae6b6e9..eb5597e 100644
--- a/test/CodeGen/X86/memset-2.ll
+++ b/test/CodeGen/X86/memset-2.ll
@@ -5,7 +5,21 @@ declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
define fastcc void @t1() nounwind {
entry:
; CHECK: t1:
-; CHECK: calll _memset
+; CHECK: pxor %xmm0, %xmm0
+; CHECK: movups %xmm0, 160
+; CHECK: movups %xmm0, 144
+; CHECK: movups %xmm0, 128
+; CHECK: movups %xmm0, 112
+; CHECK: movups %xmm0, 96
+; CHECK: movups %xmm0, 80
+; CHECK: movups %xmm0, 64
+; CHECK: movups %xmm0, 48
+; CHECK: movups %xmm0, 32
+; CHECK: movups %xmm0, 16
+; CHECK: movups %xmm0, 0
+; CHECK: movl $0, 184
+; CHECK: movl $0, 180
+; CHECK: movl $0, 176
call void @llvm.memset.i32( i8* null, i8 0, i32 188, i32 1 ) nounwind
unreachable
}