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authorChris Lattner <sabre@nondot.org>2010-09-22 00:34:38 +0000
committerChris Lattner <sabre@nondot.org>2010-09-22 00:34:38 +0000
commit8864155a35eb59fbebfd1822aaf224128b5c5d23 (patch)
tree240a0e6208ec4ca8bdaec03d51c8ede4a6fccc62 /test/CodeGen/X86/movgs.ll
parent0b79cfee1518b67f1da5cb95a44bb01fa4fad6c6 (diff)
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give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/movgs.ll')
-rw-r--r--test/CodeGen/X86/movgs.ll28
1 files changed, 26 insertions, 2 deletions
diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
index 3a24947..31c42af 100644
--- a/test/CodeGen/X86/movgs.ll
+++ b/test/CodeGen/X86/movgs.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s --check-prefix=X64
define i32 @test1() nounwind readonly {
entry:
@@ -31,3 +31,27 @@ entry:
; X64: test2:
; X64: callq *%gs:(%rdi)
+
+
+
+
+define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
+entry:
+ %0 = load i64 addrspace(256)* %p
+ %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
+ %1 = bitcast <2 x i64> %tmp2 to <8 x i16>
+ %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
+ %3 = bitcast <4 x i32> %2 to <2 x i64>
+ ret <2 x i64> %3
+
+; X32: pmovsxwd_1:
+; X32: movl 4(%esp), %eax
+; X32: pmovsxwd %gs:(%eax), %xmm0
+; X32: ret
+
+; X64: pmovsxwd_1:
+; X64: pmovsxwd %gs:(%rdi), %xmm0
+; X64: ret
+}
+
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone