Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.

e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 0 deletions

diff --git a/test/CodeGen/X86/narrow_op-2.ll b/test/CodeGen/X86/narrow_op-2.ll
new file mode 100644
index 0000000..b441794
--- /dev/null
+++ b/test/CodeGen/X86/narrow_op-2.ll
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | count 2
+; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | grep 254
+; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | grep 253
+
+	%struct.bf = type { i64, i16, i16, i32 }
+@bfi = external global %struct.bf*
+
+define void @t1() nounwind ssp {
+entry:
+	%0 = load %struct.bf** @bfi, align 8
+	%1 = getelementptr %struct.bf* %0, i64 0, i32 1
+	%2 = bitcast i16* %1 to i32*
+	%3 = load i32* %2, align 1
+	%4 = and i32 %3, -65537
+	store i32 %4, i32* %2, align 1
+	%5 = load %struct.bf** @bfi, align 8
+	%6 = getelementptr %struct.bf* %5, i64 0, i32 1
+	%7 = bitcast i16* %6 to i32*
+	%8 = load i32* %7, align 1
+	%9 = and i32 %8, -131073
+	store i32 %9, i32* %7, align 1
+	ret void
+}