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authorMichael Liao <michael.liao@intel.com>2012-09-26 08:26:25 +0000
committerMichael Liao <michael.liao@intel.com>2012-09-26 08:26:25 +0000
commit4fa2ddbb94bb7b7f67e4f4d0aac292998fbf00ed (patch)
tree02f208c5c9f1e8d1620137e6ea020395e7006348 /test/CodeGen/X86/phys_subreg_coalesce-3.ll
parent6bcdb5b9034a02901175e94e89b4815f28f2f141 (diff)
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Add SARX/SHRX/SHLX code generation support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/phys_subreg_coalesce-3.ll')
-rw-r--r--test/CodeGen/X86/phys_subreg_coalesce-3.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
index 51320dd..2a20e7a 100644
--- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
; rdar://5571034
; This requires physreg joining, %vreg13 is live everywhere: