diff options
| author | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
| commit | 6a7770b7ae43d784dec6f4d3c73ffed6166f3882 (patch) | |
| tree | 289f5949305117ae55c95f997e9f6e50b28b5ece /test/CodeGen/X86/select.ll | |
| parent | c622824ccbb74ac726c656ebc98647810d152cce (diff) | |
| download | external_llvm-6a7770b7ae43d784dec6f4d3c73ffed6166f3882.zip external_llvm-6a7770b7ae43d784dec6f4d3c73ffed6166f3882.tar.gz external_llvm-6a7770b7ae43d784dec6f4d3c73ffed6166f3882.tar.bz2 | |
Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.
Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.
On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.
Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.
The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.
Unit tests are updated so they don't depend on SD scheduling heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/select.ll')
| -rw-r--r-- | test/CodeGen/X86/select.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index 5fe2b70..cdd258d 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -34,12 +34,12 @@ bb90: ; preds = %bb84, %bb72 bb91: ; preds = %bb84 ret i32 0 ; CHECK-LABEL: test2: -; CHECK: movnew -; CHECK: movswl +; CHECK: cmovnew +; CHECK: cwtl ; ATOM-LABEL: test2: -; ATOM: movnew -; ATOM: movswl +; ATOM: cmovnew +; ATOM: cwtl } declare i1 @return_false() @@ -256,8 +256,8 @@ entry: %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone ret i8* %call ; CHECK-LABEL: test12: -; CHECK: movq $-1, %[[R:r..]] ; CHECK: mulq +; CHECK: movq $-1, %[[R:r..]] ; CHECK: cmovnoq %rax, %[[R]] ; CHECK: jmp __Znam |