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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 21:22:52 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-10 21:23:04 +0000 |
| commit | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/X86/sha.ll | |
| parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
| parent | 4c5e43da7792f75567b693105cc53e3f1992ad98 (diff) | |
| download | external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.zip external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.gz external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.bz2 | |
Merge "Update aosp/master llvm for rebase to r233350"
Diffstat (limited to 'test/CodeGen/X86/sha.ll')
| -rw-r--r-- | test/CodeGen/X86/sha.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/X86/sha.ll b/test/CodeGen/X86/sha.ll index bf81e99..fe42637 100644 --- a/test/CodeGen/X86/sha.ll +++ b/test/CodeGen/X86/sha.ll @@ -13,7 +13,7 @@ entry: define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3) ret <4 x i32> %1 ; CHECK: test_sha1rnds4rm @@ -32,7 +32,7 @@ entry: define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0) ret <4 x i32> %1 ; CHECK: test_sha1nexterm @@ -51,7 +51,7 @@ entry: define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0) ret <4 x i32> %1 ; CHECK: test_sha1msg1rm @@ -70,7 +70,7 @@ entry: define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0) ret <4 x i32> %1 ; CHECK: test_sha1msg2rm @@ -91,7 +91,7 @@ entry: define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c) ret <4 x i32> %1 ; CHECK: test_sha256rnds2rm @@ -112,7 +112,7 @@ entry: define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0) ret <4 x i32> %1 ; CHECK: test_sha256msg1rm @@ -131,7 +131,7 @@ entry: define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable { entry: - %0 = load <4 x i32>* %b + %0 = load <4 x i32>, <4 x i32>* %b %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0) ret <4 x i32> %1 ; CHECK: test_sha256msg2rm |