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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-08 08:55:49 -0700 |
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| committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-09 15:04:38 -0700 |
| commit | 4c5e43da7792f75567b693105cc53e3f1992ad98 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/X86/twoaddr-coalesce-3.ll | |
| parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
| download | external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.zip external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.gz external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.bz2 | |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
Diffstat (limited to 'test/CodeGen/X86/twoaddr-coalesce-3.ll')
| -rw-r--r-- | test/CodeGen/X86/twoaddr-coalesce-3.ll | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/test/CodeGen/X86/twoaddr-coalesce-3.ll b/test/CodeGen/X86/twoaddr-coalesce-3.ll new file mode 100644 index 0000000..33c9d46 --- /dev/null +++ b/test/CodeGen/X86/twoaddr-coalesce-3.ll @@ -0,0 +1,84 @@ +; RUN: llc < %s -march=x86-64 -relocation-model=pic | FileCheck %s +; This test is to ensure the TwoAddrInstruction pass chooses the proper operands to +; merge and generates fewer mov insns. + +@M = common global i32 0, align 4 +@total = common global i32 0, align 4 +@g = common global i32 0, align 4 + +; Function Attrs: nounwind uwtable +define void @foo() { +entry: + %0 = load i32, i32* @M, align 4 + %cmp3 = icmp sgt i32 %0, 0 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + %total.promoted = load i32, i32* @total, align 4 + br label %for.body + +; Check that only one mov will be generated in the kernel loop. +; CHECK-LABEL: foo: +; CHECK: [[LOOP1:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body +; CHECK-NOT: mov +; CHECK: movl {{.*}}, [[REG1:%[a-z0-9]+]] +; CHECK-NOT: mov +; CHECK: shrl $31, [[REG1]] +; CHECK-NOT: mov +; CHECK: jl [[LOOP1]] +for.body: ; preds = %for.body.lr.ph, %for.body + %add5 = phi i32 [ %total.promoted, %for.body.lr.ph ], [ %add, %for.body ] + %i.04 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] + %div = sdiv i32 %i.04, 2 + %add = add nsw i32 %div, %add5 + %inc = add nuw nsw i32 %i.04, 1 + %cmp = icmp slt i32 %inc, %0 + br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: ; preds = %for.body + store i32 %add, i32* @total, align 4 + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %entry + ret void +} + +; Function Attrs: nounwind uwtable +define void @goo() { +entry: + %0 = load i32, i32* @M, align 4 + %cmp3 = icmp sgt i32 %0, 0 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + %total.promoted = load i32, i32* @total, align 4 + br label %for.body + +; Check that only two mov will be generated in the kernel loop. +; CHECK-LABEL: goo: +; CHECK: [[LOOP2:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body +; CHECK-NOT: mov +; CHECK: movl {{.*}}, [[REG2:%[a-z0-9]+]] +; CHECK-NOT: mov +; CHECK: shrl $31, [[REG2]] +; CHECK-NOT: mov +; CHECK: movl {{.*}} +; CHECK: jl [[LOOP2]] +for.body: ; preds = %for.body.lr.ph, %for.body + %add5 = phi i32 [ %total.promoted, %for.body.lr.ph ], [ %add, %for.body ] + %i.04 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] + %div = sdiv i32 %i.04, 2 + %add = add nsw i32 %div, %add5 + store volatile i32 %add, i32* @g, align 4 + %inc = add nuw nsw i32 %i.04, 1 + %cmp = icmp slt i32 %inc, %0 + br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: ; preds = %for.body + store i32 %add, i32* @total, align 4 + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %entry + ret void +} + |