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author | Evan Cheng <evan.cheng@apple.com> | 2008-03-24 21:52:23 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-24 21:52:23 +0000 |
commit | 62a3f1538cf50f0373c2a5eeb440d6288604f969 (patch) | |
tree | de5c3aaf38da4e7959c9eb52eb8ed4a68f88a42d /test/CodeGen/X86/vec_extract-sse4.ll | |
parent | aec960038920c206505268eb2e8f0849364124fe (diff) | |
download | external_llvm-62a3f1538cf50f0373c2a5eeb440d6288604f969.zip external_llvm-62a3f1538cf50f0373c2a5eeb440d6288604f969.tar.gz external_llvm-62a3f1538cf50f0373c2a5eeb440d6288604f969.tar.bz2 |
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/vec_extract-sse4.ll')
-rw-r--r-- | test/CodeGen/X86/vec_extract-sse4.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/X86/vec_extract-sse4.ll b/test/CodeGen/X86/vec_extract-sse4.ll new file mode 100644 index 0000000..1ef5e88 --- /dev/null +++ b/test/CodeGen/X86/vec_extract-sse4.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t -f +; RUN: grep extractps %t | count 1 +; RUN: grep pextrd %t | count 2 +; RUN: grep pshufd %t | count 1 + +define void @t1(float* %R, <4 x float>* %P1) { + %X = load <4 x float>* %P1 + %tmp = extractelement <4 x float> %X, i32 3 + store float %tmp, float* %R + ret void +} + +define float @t2(<4 x float>* %P1) { + %X = load <4 x float>* %P1 + %tmp = extractelement <4 x float> %X, i32 2 + ret float %tmp +} + +define void @t3(i32* %R, <4 x i32>* %P1) { + %X = load <4 x i32>* %P1 + %tmp = extractelement <4 x i32> %X, i32 3 + store i32 %tmp, i32* %R + ret void +} + +define i32 @t4(<4 x i32>* %P1) { + %X = load <4 x i32>* %P1 + %tmp = extractelement <4 x i32> %X, i32 3 + ret i32 %tmp +} |