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author | Mon P Wang <wangmp@apple.com> | 2009-01-28 08:13:56 +0000 |
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committer | Mon P Wang <wangmp@apple.com> | 2009-01-28 08:13:56 +0000 |
commit | f4646d9902fcdcb121dbfbabbc2ee00bb41d7ca1 (patch) | |
tree | 85ddefbeecd56a593cbb7bc47a8e684c2578c139 /test/CodeGen/X86/vshift-2.ll | |
parent | 3becd093cc308578ca979edbbab0f76d98cef4ec (diff) | |
download | external_llvm-f4646d9902fcdcb121dbfbabbc2ee00bb41d7ca1.zip external_llvm-f4646d9902fcdcb121dbfbabbc2ee00bb41d7ca1.tar.gz external_llvm-f4646d9902fcdcb121dbfbabbc2ee00bb41d7ca1.tar.bz2 |
Added sse test patterns for r62979 and r63193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63194 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/vshift-2.ll')
-rw-r--r-- | test/CodeGen/X86/vshift-2.ll | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/test/CodeGen/X86/vshift-2.ll b/test/CodeGen/X86/vshift-2.ll new file mode 100644 index 0000000..0807174 --- /dev/null +++ b/test/CodeGen/X86/vshift-2.ll @@ -0,0 +1,64 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f +; RUN: grep psrlq %t | count 2 +; RUN: grep psrld %t | count 2 +; RUN: grep psrlw %t | count 2 + +; test vector shifts converted to proper SSE2 vector shifts when the shift +; amounts are the same. + +define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind { +entry: + %lshr = lshr <2 x i64> %val, < i64 32, i64 32 > + store <2 x i64> %lshr, <2 x i64>* %dst + ret void +} + +define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind { +entry: + %0 = insertelement <2 x i64> undef, i64 %amt, i32 0 + %1 = insertelement <2 x i64> %0, i64 %amt, i32 1 + %lshr = lshr <2 x i64> %val, %1 + store <2 x i64> %lshr, <2 x i64>* %dst + ret void +} + +define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind { +entry: + %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 > + store <4 x i32> %lshr, <4 x i32>* %dst + ret void +} + +define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind { +entry: + %0 = insertelement <4 x i32> undef, i32 %amt, i32 0 + %1 = insertelement <4 x i32> %0, i32 %amt, i32 1 + %2 = insertelement <4 x i32> %1, i32 %amt, i32 2 + %3 = insertelement <4 x i32> %2, i32 %amt, i32 3 + %lshr = lshr <4 x i32> %val, %3 + store <4 x i32> %lshr, <4 x i32>* %dst + ret void +} + + +define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind { +entry: + %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 > + store <8 x i16> %lshr, <8 x i16>* %dst + ret void +} + +define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind { +entry: + %0 = insertelement <8 x i16> undef, i16 %amt, i32 0 + %1 = insertelement <8 x i16> %0, i16 %amt, i32 1 + %2 = insertelement <8 x i16> %0, i16 %amt, i32 2 + %3 = insertelement <8 x i16> %0, i16 %amt, i32 3 + %4 = insertelement <8 x i16> %0, i16 %amt, i32 4 + %5 = insertelement <8 x i16> %0, i16 %amt, i32 5 + %6 = insertelement <8 x i16> %0, i16 %amt, i32 6 + %7 = insertelement <8 x i16> %0, i16 %amt, i32 7 + %lshr = lshr <8 x i16> %val, %7 + store <8 x i16> %lshr, <8 x i16>* %dst + ret void +}
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