diff options
| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/X86/x86-64-double-shifts-var.ll | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/X86/x86-64-double-shifts-var.ll')
| -rw-r--r-- | test/CodeGen/X86/x86-64-double-shifts-var.ll | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/test/CodeGen/X86/x86-64-double-shifts-var.ll b/test/CodeGen/X86/x86-64-double-shifts-var.ll new file mode 100644 index 0000000..5bab434 --- /dev/null +++ b/test/CodeGen/X86/x86-64-double-shifts-var.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -march=x86-64 -mcpu=athlon | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon-tbird | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon-4 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon-xp | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon-mp | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=k8 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=opteron | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon64 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon-fx | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=k8-sse3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=opteron-sse3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=athlon64-sse3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=amdfam10 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=btver1 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=btver2 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=bdver2 | FileCheck %s + +; Verify that for the X86_64 processors that are known to have poor latency +; double precision shift instructions we do not generate 'shld' or 'shrd' +; instructions. + +;uint64_t lshift(uint64_t a, uint64_t b, int c) +;{ +; return (a << c) | (b >> (64-c)); +;} + +define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone { +entry: +; CHECK-NOT: shld + %sh_prom = zext i32 %c to i64 + %shl = shl i64 %a, %sh_prom + %sub = sub nsw i32 64, %c + %sh_prom1 = zext i32 %sub to i64 + %shr = lshr i64 %b, %sh_prom1 + %or = or i64 %shr, %shl + ret i64 %or +} + +;uint64_t rshift(uint64_t a, uint64_t b, int c) +;{ +; return (a >> c) | (b << (64-c)); +;} + +define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone { +entry: +; CHECK-NOT: shrd + %sh_prom = zext i32 %c to i64 + %shr = lshr i64 %a, %sh_prom + %sub = sub nsw i32 64, %c + %sh_prom1 = zext i32 %sub to i64 + %shl = shl i64 %b, %sh_prom1 + %or = or i64 %shl, %shr + ret i64 %or +} + + |