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| author | Andrew Trick <atrick@apple.com> | 2012-02-10 04:10:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-10 04:10:36 +0000 |
| commit | 8dd26253f54247e77e5accfdd70e7b4bf27b39c2 (patch) | |
| tree | df14b7b3cec3b603bc5feb7070a05f00eb83d4a5 /test/CodeGen/X86 | |
| parent | 16f72dd68653bd4984363483cfc15ce91fa613d4 (diff) | |
| download | external_llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.zip external_llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.tar.gz external_llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.tar.bz2 | |
RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline.
Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
CodeGen transformation passes are never "required" as an analysis
ProcessImplicitDefs does not require LiveVariables.
We have a plan to massively simplify some of the early passes within the regalloc superpass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
| -rw-r--r-- | test/CodeGen/X86/2008-05-21-CoalescerBug.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/fast-isel-bc.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/inline-asm-tied.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/object-size.ll | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll index f4f4195..ac167b0 100644 --- a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=basic | grep mov | count 5 +; RUN: llc < %s -march=x86 -O0 -fast-isel=false -optimize-regalloc -regalloc=basic | grep mov | count 5 ; PR2343 %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/CodeGen/X86/fast-isel-bc.ll b/test/CodeGen/X86/fast-isel-bc.ll index 193e436..8ac15cd 100644 --- a/test/CodeGen/X86/fast-isel-bc.ll +++ b/test/CodeGen/X86/fast-isel-bc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -regalloc=basic -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s +; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s ; PR4684 target datalayout = diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll index de6500d..91576fb 100644 --- a/test/CodeGen/X86/inline-asm-tied.ll +++ b/test/CodeGen/X86/inline-asm-tied.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s ; rdar://6992609 ; CHECK: movl [[EDX:%e..]], 4(%esp) diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll index 082d20c..8f1eabd 100644 --- a/test/CodeGen/X86/object-size.ll +++ b/test/CodeGen/X86/object-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -regalloc=basic < %s -march=x86-64 | FileCheck %s -check-prefix=X64 +; RUN: llc -O0 < %s -march=x86-64 | FileCheck %s -check-prefix=X64 ; ModuleID = 'ts.c' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" |