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authorDan Gohman <gohman@apple.com>2009-08-26 14:59:13 +0000
committerDan Gohman <gohman@apple.com>2009-08-26 14:59:13 +0000
commitaf70e5c676140a55ec619f552c8fd76b7edf3c6d (patch)
treedaaa20890ab20b911913f65f5b0f98e309c53883 /test/CodeGen/X86
parent2385e0e22ca482f2896dfa975a08db2f54926c09 (diff)
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Don't use INSERT_SUBREG to model anyext operations on x86-64, as it
leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80099 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
-rw-r--r--test/CodeGen/X86/anyext.ll18
-rw-r--r--test/CodeGen/X86/ins_subreg_coalesce-1.ll2
2 files changed, 19 insertions, 1 deletions
diff --git a/test/CodeGen/X86/anyext.ll b/test/CodeGen/X86/anyext.ll
new file mode 100644
index 0000000..c5f03ab
--- /dev/null
+++ b/test/CodeGen/X86/anyext.ll
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep movzbl | count 2
+
+; Use movzbl to avoid partial-register updates.
+
+define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
+ %q = trunc i32 %p to i8
+ %r = udiv i8 %q, %x
+ %s = zext i8 %r to i32
+ %t = and i32 %s, 1
+ ret i32 %t
+}
+define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
+ %q = trunc i32 %p to i16
+ %r = udiv i16 %q, %x
+ %s = zext i16 %r to i32
+ %t = and i32 %s, 1
+ ret i32 %t
+}
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
index 863cda9..a0347ea 100644
--- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll
+++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 2
+; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 3
define fastcc i32 @sqlite3ExprResolveNames() nounwind {
entry: