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| author | Richard Osborne <richard@xmos.com> | 2011-03-15 13:45:47 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-03-15 13:45:47 +0000 |
| commit | 5aad8b3e7884b60811ee4c338597d56f732336fb (patch) | |
| tree | 37d7eb655b60d8b188de0362cbe22bf0315b6aaa /test/CodeGen/XCore | |
| parent | 625eec10fef5449f709ecd7a4e348aa94b29aef8 (diff) | |
| download | external_llvm-5aad8b3e7884b60811ee4c338597d56f732336fb.zip external_llvm-5aad8b3e7884b60811ee4c338597d56f732336fb.tar.gz external_llvm-5aad8b3e7884b60811ee4c338597d56f732336fb.tar.bz2 | |
Add XCore intrinsics for getps, setps, setsr and clrsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/XCore')
| -rw-r--r-- | test/CodeGen/XCore/ps-intrinsics.ll | 18 | ||||
| -rw-r--r-- | test/CodeGen/XCore/sr-intrinsics.ll | 18 |
2 files changed, 36 insertions, 0 deletions
diff --git a/test/CodeGen/XCore/ps-intrinsics.ll b/test/CodeGen/XCore/ps-intrinsics.ll new file mode 100644 index 0000000..92b26c7 --- /dev/null +++ b/test/CodeGen/XCore/ps-intrinsics.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +declare i32 @llvm.xcore.getps(i32) +declare void @llvm.xcore.setps(i32, i32) + +define i32 @getps(i32 %reg) nounwind { +; CHECK: getps: +; CHECK: get r0, ps[r0] + %result = call i32 @llvm.xcore.getps(i32 %reg) + ret i32 %result +} + + +define void @setps(i32 %reg, i32 %value) nounwind { +; CHECK: setps: +; CHECK: set ps[r0], r1 + call void @llvm.xcore.setps(i32 %reg, i32 %value) + ret void +} diff --git a/test/CodeGen/XCore/sr-intrinsics.ll b/test/CodeGen/XCore/sr-intrinsics.ll new file mode 100644 index 0000000..e12ed03 --- /dev/null +++ b/test/CodeGen/XCore/sr-intrinsics.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +declare void @llvm.xcore.setsr(i32) +declare void @llvm.xcore.clrsr(i32) + +define void @setsr() nounwind { +; CHECK: setsr: +; CHECK: setsr 128 + call void @llvm.xcore.setsr(i32 128) + ret void +} + + +define void @clrsr() nounwind { +; CHECK: clrsr: +; CHECK: clrsr 128 + call void @llvm.xcore.clrsr(i32 128) + ret void +} |