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author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-02-04 15:52:32 +0000 |
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committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-02-04 15:52:32 +0000 |
commit | 0d3731478e6242cceae7c006a071b8b17f7fd298 (patch) | |
tree | c01bae67a0466b124c6f2d4f0da3b3f993243f39 /test/CodeGen | |
parent | 42a68443a15d74ada014ad2c8a2349fe134a44f3 (diff) | |
download | external_llvm-0d3731478e6242cceae7c006a071b8b17f7fd298.zip external_llvm-0d3731478e6242cceae7c006a071b8b17f7fd298.tar.gz external_llvm-0d3731478e6242cceae7c006a071b8b17f7fd298.tar.bz2 |
Disable a couple more vector splat optimizations on PPC.
I didn't see those because the test case used "not grep". FileCheck the test and
XFAIL it, preserving the old optimization, so this can be fixed eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/PowerPC/vec_constants.ll | 42 |
1 files changed, 41 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index 399f19f..71aa359 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI +; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s +; XFAIL: * define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] @@ -13,32 +14,71 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] store <4 x float> %tmp13, <4 x float>* %P3 ret void + +; CHECK: test1: +; CHECK-NOT: CPI } define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > + +; CHECK: test_30: +; CHECK: vspltisw +; CHECK-NEXT: vadduwm +; CHECK-NEXT: blr } define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > + +; CHECK: test_29: +; CHECK: vspltisw +; CHECK-NEXT: vspltisw +; CHECK-NEXT: vsubuwm +; CHECK-NEXT: blr } define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > + +; CHECK: test_n30: +; CHECK: vspltish +; CHECK-NEXT: vadduhm +; CHECK-NEXT: blr } define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > + +; CHECK: test_n104: +; CHECK: vspltisb +; CHECK-NEXT: vslb +; CHECK-NEXT: blr } define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > + +; CHECK: test_vsldoi: +; CHECK: vspltisw +; CHECK-NEXT: vsldoi +; CHECK-NEXT: blr } define <8 x i16> @test_vsldoi_65023() nounwind { ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > + +; CHECK: test_vsldoi_65023: +; CHECK: vspltish +; CHECK-NEXT: vsldoi +; CHECK-NEXT: blr } define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > + +; CHECK: test_rol: +; CHECK: vspltisw +; CHECK-NEXT: vrlw +; CHECK-NEXT: blr } |