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author | Evan Cheng <evan.cheng@apple.com> | 2009-09-28 05:28:43 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-09-28 05:28:43 +0000 |
commit | 0e6b590b91fcf6d49d2c25196f5053ce285e17f5 (patch) | |
tree | da1b9e6b4a8e12e2409e5bf29c19f5d62e836473 /test/CodeGen | |
parent | 17167be9487025c90ed79ccc7d09f684be8a797a (diff) | |
download | external_llvm-0e6b590b91fcf6d49d2c25196f5053ce285e17f5.zip external_llvm-0e6b590b91fcf6d49d2c25196f5053ce285e17f5.tar.gz external_llvm-0e6b590b91fcf6d49d2c25196f5053ce285e17f5.tar.bz2 |
Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82968 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/ARM/2009-09-27-CoalescerBug.ll | 24 | ||||
-rw-r--r-- | test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/X86/sink-hoist.ll | 2 |
3 files changed, 25 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll b/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll new file mode 100644 index 0000000..ea2693a --- /dev/null +++ b/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 +; PR5055 + +module asm ".globl\09__aeabi_f2lz" +module asm ".set\09__aeabi_f2lz, __fixsfdi" +module asm "" + +define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind { +entry: + %0 = fcmp olt float %a, 0.000000e+00 ; <i1> [#uses=1] + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry + %1 = fsub float -0.000000e+00, %a ; <float> [#uses=1] + %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; <i64> [#uses=1] + %3 = sub i64 0, %2 ; <i64> [#uses=1] + ret i64 %3 + +bb1: ; preds = %entry + %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; <i64> [#uses=1] + ret i64 %4 +} + +declare arm_aapcs_vfpcc i64 @__fixunssfdi(float) diff --git a/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll b/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll index 412c669..0b731dc 100644 --- a/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll +++ b/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=bfin -verify-machineinstrs -; XFAIL: * ; When joining live intervals of sub-registers, an MBB live-in list is not ; updated properly. The register scavenger asserts on an undefined register. diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 24f2f94..66582ec 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -7,7 +7,7 @@ ; CHECK: foo: ; CHECK-NEXT: divsd -; CHECK-NEXT: testb $1, %dil +; CHECK: testb $1, %dil ; CHECK-NEXT: jne define double @foo(double %x, double %y, i1 %c) nounwind { |