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authorJyotsna Verma <jverma@codeaurora.org>2013-03-05 19:04:47 +0000
committerJyotsna Verma <jverma@codeaurora.org>2013-03-05 19:04:47 +0000
commit18daead3ff41902a61ff3344cfa77ac8aba5586d (patch)
tree5e75c3bbb9d810676692cbc580dccbef4e2c7597 /test/CodeGen
parent6936ebd700d8195cfed39baa21230ee736fe1316 (diff)
downloadexternal_llvm-18daead3ff41902a61ff3344cfa77ac8aba5586d.zip
external_llvm-18daead3ff41902a61ff3344cfa77ac8aba5586d.tar.gz
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Hexagon: Expand addc, adde, subc and sube.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/Hexagon/adde.ll34
-rw-r--r--test/CodeGen/Hexagon/sube.ll29
2 files changed, 63 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll
new file mode 100644
index 0000000..9cee3e2
--- /dev/null
+++ b/test/CodeGen/Hexagon/adde.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK: r{{[0-9]+:[0-9]+}} = #0
+; CHECK: r{{[0-9]+:[0-9]+}} = #1
+; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+
+
+define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128
+ %tmp23 = zext i64 %AH to i128
+ %tmp4 = shl i128 %tmp23, 64
+ %tmp5 = or i128 %tmp4, %tmp1
+ %tmp67 = zext i64 %BL to i128
+ %tmp89 = zext i64 %BH to i128
+ %tmp11 = shl i128 %tmp89, 64
+ %tmp12 = or i128 %tmp11, %tmp67
+ %tmp15 = add i128 %tmp12, %tmp5
+ %tmp1617 = trunc i128 %tmp15 to i64
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64
+ %tmp2122 = trunc i128 %tmp21 to i64
+ store i64 %tmp2122, i64* %RH
+ ret void
+} \ No newline at end of file
diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll
new file mode 100644
index 0000000..84172e9
--- /dev/null
+++ b/test/CodeGen/Hexagon/sube.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK: r{{[0-9]+:[0-9]+}} = #0
+; CHECK: r{{[0-9]+:[0-9]+}} = #1
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
+
+define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128
+ %tmp23 = zext i64 %AH to i128
+ %tmp4 = shl i128 %tmp23, 64
+ %tmp5 = or i128 %tmp4, %tmp1
+ %tmp67 = zext i64 %BL to i128
+ %tmp89 = zext i64 %BH to i128
+ %tmp11 = shl i128 %tmp89, 64
+ %tmp12 = or i128 %tmp11, %tmp67
+ %tmp15 = sub i128 %tmp5, %tmp12
+ %tmp1617 = trunc i128 %tmp15 to i64
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64
+ %tmp2122 = trunc i128 %tmp21 to i64
+ store i64 %tmp2122, i64* %RH
+ ret void
+} \ No newline at end of file