Add 32 bit and reg-imm and disable invalid patterns for now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 25 insertions, 10 deletions

diff --git a/test/CodeGen/SystemZ/02-RetAndImm.ll b/test/CodeGen/SystemZ/02-RetAndImm.ll
index f19ceab..5655e99 100644
--- a/test/CodeGen/SystemZ/02-RetAndImm.ll
+++ b/test/CodeGen/SystemZ/02-RetAndImm.ll
@@ -1,3 +1,4 @@
+; XFAIL: *
 ; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1
 ; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 1
 ; RUN: llvm-as < %s | llc -march=systemz | grep nihl | count 1
diff --git a/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
index 86fe94a..2eb1640 100644
--- a/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
+++ b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
@@ -1,3 +1,4 @@
+; XFAIL: *
 ; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 3
 ; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 3
 
diff --git a/test/CodeGen/SystemZ/03-RetAndSubreg.ll b/test/CodeGen/SystemZ/03-RetAndSubreg.ll
index 8b65757..465d118 100644
--- a/test/CodeGen/SystemZ/03-RetAndSubreg.ll
+++ b/test/CodeGen/SystemZ/03-RetAndSubreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 3
+; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 4
 
 define i32 @foo(i32 %a, i32 %b) {
 entry:
diff --git a/test/CodeGen/SystemZ/03-RetArgSubreg.ll b/test/CodeGen/SystemZ/03-RetArgSubreg.ll
index a31adbc..1135fbd 100644
--- a/test/CodeGen/SystemZ/03-RetArgSubreg.ll
+++ b/test/CodeGen/SystemZ/03-RetArgSubreg.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 2
-; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
-; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep lgr   | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep lgfr  | count 1
 
 
 define i32 @foo(i32 %a, i32 %b) {
diff --git a/test/CodeGen/SystemZ/03-RetOrSubreg.ll b/test/CodeGen/SystemZ/03-RetOrSubreg.ll
index d0598fc..86078f6 100644
--- a/test/CodeGen/SystemZ/03-RetOrSubreg.ll
+++ b/test/CodeGen/SystemZ/03-RetOrSubreg.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=systemz | grep ogr  | count 3
-; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
-; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep ogr   | count 3
+; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep lgfr  | count 1
 
 
 define i32 @foo(i32 %a, i32 %b) {
diff --git a/test/CodeGen/SystemZ/03-RetXorSubreg.ll b/test/CodeGen/SystemZ/03-RetXorSubreg.ll
index e8caba1..9b5eb9b 100644
--- a/test/CodeGen/SystemZ/03-RetXorSubreg.ll
+++ b/test/CodeGen/SystemZ/03-RetXorSubreg.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=systemz | grep xgr  | count 3
-; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
-; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep xgr   | count 3
+; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep lgfr  | count 1
 
 
 define i32 @foo(i32 %a, i32 %b) {
diff --git a/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll b/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll
new file mode 100644
index 0000000..cf70af6
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 2
+
+define i32 @gnu_dev_major(i64 %__dev) nounwind readnone {
+entry:
+        %shr = lshr i64 %__dev, 8               ; <i64> [#uses=1]
+        %shr8 = trunc i64 %shr to i32           ; <i32> [#uses=1]
+        %shr2 = lshr i64 %__dev, 32             ; <i64> [#uses=1]
+        %conv = trunc i64 %shr2 to i32          ; <i32> [#uses=1]
+        %and3 = and i32 %conv, -4096            ; <i32> [#uses=1]
+        %and6 = and i32 %shr8, 4095             ; <i32> [#uses=1]
+        %conv5 = or i32 %and6, %and3            ; <i32> [#uses=1]
+        ret i32 %conv5
+}