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authorManman Ren <mren@apple.com>2012-10-30 22:15:38 +0000
committerManman Ren <mren@apple.com>2012-10-30 22:15:38 +0000
commit4c74a956b2621bb7bb1df0b2f7571060eb095464 (patch)
treeb3bc0ee117a8be8e88367fb60d45ced867132a4d /test/CodeGen
parenta368b89f2842530d07c0ac8e3b533882e165f197 (diff)
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X86 MMX: optimize transfer from mmx to i32
We used to generate a store (movq) + a load. Now we use movd. rdar://9946746 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167056 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/X86/mmx-builtins.ll14
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/X86/mmx-builtins.ll b/test/CodeGen/X86/mmx-builtins.ll
index 8b7200d..a8d33f4 100644
--- a/test/CodeGen/X86/mmx-builtins.ll
+++ b/test/CodeGen/X86/mmx-builtins.ll
@@ -1043,6 +1043,20 @@ entry:
ret i64 %5
}
+define i32 @test21_2(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: test21_2
+; CHECK: pshufw
+; CHECK: movd
+entry:
+ %0 = bitcast <1 x i64> %a to <4 x i16>
+ %1 = bitcast <4 x i16> %0 to x86_mmx
+ %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
+ %3 = bitcast x86_mmx %2 to <4 x i16>
+ %4 = bitcast <4 x i16> %3 to <2 x i32>
+ %5 = extractelement <2 x i32> %4, i32 0
+ ret i32 %5
+}
+
declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx) nounwind readnone
define i64 @test20(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {