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| author | Bob Wilson <bob.wilson@apple.com> | 2010-09-29 17:54:10 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-09-29 17:54:10 +0000 |
| commit | 7122ba7efb5430d724ed3a0ac86fa7f7185b43ba (patch) | |
| tree | 221bcb00ba6237d7faba0d6bd836515b6782b2cd /test/CodeGen | |
| parent | 6cded231a3a748e4fb1339891c81d385058e571f (diff) | |
| download | external_llvm-7122ba7efb5430d724ed3a0ac86fa7f7185b43ba.zip external_llvm-7122ba7efb5430d724ed3a0ac86fa7f7185b43ba.tar.gz external_llvm-7122ba7efb5430d724ed3a0ac86fa7f7185b43ba.tar.bz2 | |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/align.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll index d4d0128..d57c159 100644 --- a/test/CodeGen/ARM/align.ll +++ b/test/CodeGen/ARM/align.ll @@ -22,7 +22,7 @@ @e = global i64 4 ;ELF: .align 3 ;ELF: e -;DARWIN: .align 2 +;DARWIN: .align 3 ;DARWIN: _e: @f = global float 5.0 @@ -34,7 +34,7 @@ @g = global double 6.0 ;ELF: .align 3 ;ELF: g: -;DARWIN: .align 2 +;DARWIN: .align 3 ;DARWIN: _g: @bar = common global [75 x i8] zeroinitializer, align 128 |