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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-11-12 22:39:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-11-12 22:39:34 +0000 |
| commit | 7f67091259270c1e84919f3c6f9f4241e1301598 (patch) | |
| tree | 10dacf39a5e3f36652d547f04b6d30e7288413e6 /test/CodeGen | |
| parent | 2eda9458ea8842f589f5fa33eb088f5942f4c8a8 (diff) | |
| download | external_llvm-7f67091259270c1e84919f3c6f9f4241e1301598.zip external_llvm-7f67091259270c1e84919f3c6f9f4241e1301598.tar.gz external_llvm-7f67091259270c1e84919f3c6f9f4241e1301598.tar.bz2 | |
Linear scan is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144472 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/str_pre-2.ll | 1 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/ldr-str-imm12.ll | 10 | ||||
| -rw-r--r-- | test/CodeGen/X86/2008-09-18-inline-asm-2.ll | 1 | ||||
| -rw-r--r-- | test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll | 2 |
4 files changed, 6 insertions, 8 deletions
diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index f4e3a44..983ba45 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=linearscan | FileCheck %s ; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s ; The greedy register allocator uses a single CSR here, invalidating the test. diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 4597ba5..36544d1 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -regalloc=linearscan | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s ; rdar://7352504 ; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]". @@ -46,10 +46,10 @@ bb119: ; preds = %bb20, %bb20 bb420: ; preds = %bb20, %bb20 ; CHECK: bb420 -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp] -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4] -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8] -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index 511c7b5..6867ae7 100644 --- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -march=x86 -regalloc=linearscan | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index e904b1c..9f5a8c5 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -asm-verbose=false \ -; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false -regalloc=linearscan < %s | \ +; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false -regalloc=basic < %s | \ ; RUN: FileCheck %s ; rdar://6808032 |