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| author | Evan Cheng <evan.cheng@apple.com> | 2010-06-18 23:09:54 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-06-18 23:09:54 +0000 |
| commit | 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 (patch) | |
| tree | e3d4931d8b43804f50e973d4c6763ccdb01cbbc3 /test/CodeGen | |
| parent | ef6eb9c7ab7967790566c5e2d47977d89fc060ee (diff) | |
| download | external_llvm-86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92.zip external_llvm-86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92.tar.gz external_llvm-86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92.tar.bz2 | |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/ifcvt2.ll | 15 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-cbnz.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-ifcvt2.ll | 1 |
3 files changed, 12 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index d9cac80..7b9d0cf 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep bxlt %t | count 1 -; RUN: grep bxgt %t | count 1 -; RUN: not grep bxge %t -; RUN: not grep bxle %t +; RUN: llc < %s -march=arm | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t1: +; CHECK: bxlt lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = or i1 %tmp5, %tmp2 @@ -21,6 +19,13 @@ UnifiedReturnBlock: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t2: +; CHECK: bxgt lr +; CHECK: cmp +; CHECK: addge +; CHECK: subge +; CHECK-NOT: bxge lr +; CHECK: bx lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = and i1 %tmp5, %tmp2 diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll index 4f4c9af..10a4985 100644 --- a/test/CodeGen/Thumb2/thumb2-cbnz.ll +++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll @@ -21,7 +21,7 @@ bb7: ; preds = %bb3 bb9: ; preds = %bb7 ; CHECK: cmp r0, #0 -; CHECK-NEXT: cmp r0, #0 +; CHECK: cmp r0, #0 ; CHECK-NEXT: cbnz %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll index 4af492c..2c57348 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll @@ -32,6 +32,7 @@ entry: ; CHECK: it eq ; CHECK: cmpeq ; CHECK: bne +; CHECK: cmp ; CHECK: itt eq ; CHECK: moveq ; CHECK: popeq |