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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-18 10:04:39 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-18 10:04:39 +0000 |
| commit | 86a791284ae473a8820144be77ce92db8bd3028e (patch) | |
| tree | 3d3ffbee82e1fad9a266ba29cc14990b48a24eb8 /test/CodeGen | |
| parent | 44ff5f5435c60558b47d975655385f15b0dee01c (diff) | |
| download | external_llvm-86a791284ae473a8820144be77ce92db8bd3028e.zip external_llvm-86a791284ae473a8820144be77ce92db8bd3028e.tar.gz external_llvm-86a791284ae473a8820144be77ce92db8bd3028e.tar.bz2 | |
Remove all traces of v2[i,f]32 on SPU.
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are
expanded. This causes changes to some dejagnu tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/CellSPU/arg_ret.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/v2f32.ll | 8 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/v2i32.ll | 10 |
3 files changed, 10 insertions, 10 deletions
diff --git a/test/CodeGen/CellSPU/arg_ret.ll b/test/CodeGen/CellSPU/arg_ret.ll index db8ff10..743292a 100644 --- a/test/CodeGen/CellSPU/arg_ret.ll +++ b/test/CodeGen/CellSPU/arg_ret.ll @@ -26,7 +26,7 @@ define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm ) define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) { -;CHEKC: lqd $75, 80($sp) +;CHECK: lqd $75, 80($sp) ;CHECK: lr $3, $4 ret %paramstruct %prm } diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index 3249631..b81c0cd 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -9,7 +9,7 @@ define %vec @test_ret(%vec %param) define %vec @test_add(%vec %param) { -;CHECK: fa $3, $3, $3 +;CHECK: fa {{\$.}}, $3, $3 %1 = fadd %vec %param, %param ;CHECK: bi $lr ret %vec %1 @@ -17,7 +17,7 @@ define %vec @test_add(%vec %param) define %vec @test_sub(%vec %param) { -;CHECK: fs $3, $3, $3 +;CHECK: fs {{\$.}}, $3, $3 %1 = fsub %vec %param, %param ;CHECK: bi $lr @@ -26,7 +26,7 @@ define %vec @test_sub(%vec %param) define %vec @test_mul(%vec %param) { -;CHECK: fm $3, $3, $3 +;CHECK: fm {{\$.}}, $3, $3 %1 = fmul %vec %param, %param ;CHECK: bi $lr @@ -47,7 +47,7 @@ define void @test_store(%vec %val, %vec* %ptr){ ;CHECK: stqd store %vec undef, %vec* null -;CHECK: stqd $3, 0($4) +;CHECK: stqd $3, 0(${{.}}) ;CHECK: bi $lr store %vec %val, %vec* %ptr ret void diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll index ca8af6a..dd51be5 100644 --- a/test/CodeGen/CellSPU/v2i32.ll +++ b/test/CodeGen/CellSPU/v2i32.ll @@ -9,7 +9,7 @@ define %vec @test_ret(%vec %param) define %vec @test_add(%vec %param) { -;CHECK: a $3, $3, $3 +;CHECK: a {{\$.}}, $3, $3 %1 = add %vec %param, %param ;CHECK: bi $lr ret %vec %1 @@ -17,7 +17,7 @@ define %vec @test_add(%vec %param) define %vec @test_sub(%vec %param) { -;CHECK: sf $3, $4, $3 +;CHECK: sf {{\$.}}, $4, $3 %1 = sub %vec %param, <i32 1, i32 1> ;CHECK: bi $lr @@ -28,8 +28,8 @@ define %vec @test_mul(%vec %param) { ;CHECK: mpyu ;CHECK: mpyh -;CHECK: a -;CHECK: a $3 +;CHECK: a {{\$., \$., \$.}} +;CHECK: a {{\$., \$., \$.}} %1 = mul %vec %param, %param ;CHECK: bi $lr @@ -57,7 +57,7 @@ define i32 @test_extract() { define void @test_store( %vec %val, %vec* %ptr) { -;CHECK: stqd $3, 0($4) +;CHECK: stqd $3, 0(${{.}}) ;CHECK: bi $lr store %vec %val, %vec* %ptr ret void |