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| author | Michael Liao <michael.liao@intel.com> | 2013-06-05 18:12:26 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-06-05 18:12:26 +0000 |
| commit | 9a508ef64a194f0f4a3362c55a6e33bec18b7554 (patch) | |
| tree | 6bfbf25677071a5f26b10630d09ac4bb6ba67f63 /test/CodeGen | |
| parent | bcb1ea8ef62fba49d0e634e1943f829687323314 (diff) | |
| download | external_llvm-9a508ef64a194f0f4a3362c55a6e33bec18b7554.zip external_llvm-9a508ef64a194f0f4a3362c55a6e33bec18b7554.tar.gz external_llvm-9a508ef64a194f0f4a3362c55a6e33bec18b7554.tar.bz2 | |
[PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."
---
[1] http://software.intel.com/sites/default/files/319433-014.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/avx2-gather.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx2-gather.ll b/test/CodeGen/X86/avx2-gather.ll new file mode 100644 index 0000000..ee50c45 --- /dev/null +++ b/test/CodeGen/X86/avx2-gather.ll @@ -0,0 +1,18 @@ +; RUN: not llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s + +declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, i8*, + <4 x i32>, <4 x float>, i8) nounwind readonly + +define <4 x float> @test_x86_avx2_gather_d_ps(i8* %a1, + <4 x i32> %idx, <4 x float> %mask) { + %res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> undef, + i8* %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ; + ret <4 x float> %res +} + +; CHECK: test_x86_avx2_gather_d_ps +; CHECK: vgatherdps +; CHECK-NOT: [[DST]] +; CHECK: [[DST:%xmm[0-9]+]]{{$}} +; CHECK: ret |