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author | Silviu Baranga <silviu.baranga@arm.com> | 2013-03-27 12:38:44 +0000 |
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committer | Silviu Baranga <silviu.baranga@arm.com> | 2013-03-27 12:38:44 +0000 |
commit | a210db781f17b5ab8e2b71d53276153a9d15eead (patch) | |
tree | c86702560e31e81e948c5014c6370be78c191deb /test/CodeGen | |
parent | 0f680703ebb1352cccbcec8ada1e0ae7fbc26d3c (diff) | |
download | external_llvm-a210db781f17b5ab8e2b71d53276153a9d15eead.zip external_llvm-a210db781f17b5ab8e2b71d53276153a9d15eead.tar.gz external_llvm-a210db781f17b5ab8e2b71d53276153a9d15eead.tar.bz2 |
Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/ARM/a15-SD-dep.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/ARM/a15-partial-update.ll | 38 |
2 files changed, 41 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll index 17e3eba..a52468e 100644 --- a/test/CodeGen/ARM/a15-SD-dep.ll +++ b/test/CodeGen/ARM/a15-SD-dep.ll @@ -5,7 +5,7 @@ ; CHECK-DISABLED: t1: define <2 x float> @t1(float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] - ; CHECK-DISABLED: vmov.32 d0[1], r{{.}} + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] %i1 = insertelement <2 x float> undef, float %f, i32 1 %i2 = fadd <2 x float> %i1, %i1 ret <2 x float> %i2 @@ -15,7 +15,7 @@ define <2 x float> @t1(float %f) { ; CHECK-DISABLED: t2: define <4 x float> @t2(float %g, float %f) { ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0] - ; CHECK-DISABLED: vmov.32 d0[1], r{{.}} + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] %i1 = insertelement <4 x float> undef, float %f, i32 1 %i2 = fadd <4 x float> %i1, %i1 ret <4 x float> %i2 @@ -25,6 +25,7 @@ define <4 x float> @t2(float %g, float %f) { ; CHECK-DISABLED: t3: define arm_aapcs_vfpcc <2 x float> @t3(float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] %i1 = insertelement <2 x float> undef, float %f, i32 1 %i2 = fadd <2 x float> %i1, %i1 ret <2 x float> %i2 diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll new file mode 100644 index 0000000..6306790 --- /dev/null +++ b/test/CodeGen/ARM/a15-partial-update.ll @@ -0,0 +1,38 @@ +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s + +; CHECK: t1: +define <2 x float> @t1(float* %A, <2 x float> %B) { +; The generated code for this test uses a vld1.32 instruction +; to write the lane 1 of a D register containing the value of +; <2 x float> %B. Since the D register is defined, it would +; be incorrect to fully write it (with a vmov.f64) before the +; vld1.32 instruction. The test checks that a vmov.f64 was not +; generated. + +; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}}, + %tmp2 = load float* %A, align 4 + %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1 + ret <2 x float> %tmp3 +} + +; CHECK: t2: +define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) { +entry: + br label %loop +loop: +; The code generated by this test uses a vld1.32 instruction. +; We check that a dependency breaking vmov* instruction was +; generated. + +; CHECK: vmov.{{.*}} d{{[0-9]+}}, + %oldcount = phi i32 [0, %entry], [%newcount, %loop] + %newcount = add i32 %oldcount, 1 + %p1 = getelementptr <4 x i8> *%in, i32 %newcount + %p2 = getelementptr <4 x i8> *%out, i32 %newcount + %tmp1 = load <4 x i8> *%p1, align 4 + store <4 x i8> %tmp1, <4 x i8> *%p2 + %cmp = icmp eq i32 %newcount, %n + br i1 %cmp, label %loop, label %ret +ret: + ret void +} |