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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-05 03:43:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-05 03:43:06 +0000 |
| commit | ad7ecc65b1b1d6466ff035168c86f208a91aa1b4 (patch) | |
| tree | 50680fbe0211eb5a6b6433816f028cc4e09572fc /test/CodeGen | |
| parent | 23a22cdedda691b5ed39f75bc1a846fd890f07fb (diff) | |
| download | external_llvm-ad7ecc65b1b1d6466ff035168c86f208a91aa1b4.zip external_llvm-ad7ecc65b1b1d6466ff035168c86f208a91aa1b4.tar.gz external_llvm-ad7ecc65b1b1d6466ff035168c86f208a91aa1b4.tar.bz2 | |
R600: Make sure to schedule AR register uses and defs in the same clause
Reviewed-by: vljn at ovi.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/R600/indirect-addressing.ll | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/R600/indirect-addressing.ll b/test/CodeGen/R600/indirect-addressing.ll new file mode 100644 index 0000000..7291cb4 --- /dev/null +++ b/test/CodeGen/R600/indirect-addressing.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This test checks that uses and defs of the AR register happen in the same +; instruction clause. + +; CHECK: @mova_same_clause +; CHECK: MOVA_INT +; CHECK-NOT: ALU clause +; CHECK: 0 + AR.x +; CHECK: MOVA_INT +; CHECK-NOT: ALU clause +; CHECK: 0 + AR.x + +define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %in, i32 1 + %1 = load i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} |