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| author | Evan Cheng <evan.cheng@apple.com> | 2011-04-19 00:04:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-04-19 00:04:03 +0000 |
| commit | b58a340fa2affa0da27a46c94dd49ba079c9343c (patch) | |
| tree | e52d498496e7fca2b0f6a6508e1dd7b943b6b4d8 /test/CodeGen | |
| parent | 05a5ff1f00c30a68a151342bf7c47bf86d555d57 (diff) | |
| download | external_llvm-b58a340fa2affa0da27a46c94dd49ba079c9343c.zip external_llvm-b58a340fa2affa0da27a46c94dd49ba079c9343c.tar.gz external_llvm-b58a340fa2affa0da27a46c94dd49ba079c9343c.tar.bz2 | |
Do not lose mem_operands while lowering VLD / VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/vld1.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vldlane.ll | 10 |
2 files changed, 7 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 02e543c..e524395 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -133,8 +133,6 @@ declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly ; Do not crash if the vld1 result is not used. define void @unused_vld1_result() { entry: -;CHECK: unused_vld1_result -;CHECK: vld1.32 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) call void @llvm.trap() unreachable diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 68dd503..805aad5 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -491,7 +491,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) -define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { ;CHECK: test_qqqq_regsequence_subreg ;CHECK: vld3.16 %tmp63 = extractvalue [6 x i64] %b, 5 @@ -500,8 +500,12 @@ define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { %ins67 = or i128 %tmp65, 0 %tmp78 = bitcast i128 %ins67 to <8 x i16> %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) - call void @llvm.trap() - unreachable + %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0 + %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1 + %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2 + %tmp6 = add <8 x i16> %tmp3, %tmp4 + %tmp7 = add <8 x i16> %tmp5, %tmp6 + ret <8 x i16> %tmp7 } declare void @llvm.trap() nounwind |