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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 19:28:31 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 19:28:31 +0000 |
| commit | b8720787015dc73d8a050b063366be6c3ad01946 (patch) | |
| tree | 3d4a03ae7359619d56d097bf1644726d6735479e /test/CodeGen | |
| parent | f86c00f1f89082c800dbb78870fc5537eb3702f6 (diff) | |
| download | external_llvm-b8720787015dc73d8a050b063366be6c3ad01946.zip external_llvm-b8720787015dc73d8a050b063366be6c3ad01946.tar.gz external_llvm-b8720787015dc73d8a050b063366be6c3ad01946.tar.bz2 | |
Ensure CopyToReg nodes are always glued to the call instruction.
The CopyToReg nodes that set up the argument registers before a call
must be glued to the call instruction. Otherwise, the scheduler may emit
the physreg copies long before the call, causing long live ranges for
the fixed registers.
Besides disabling good register allocation, that can also expose
problems when EmitInstrWithCustomInserter() splits a basic block during
the live range of a physreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/crash.ll | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/tailcall-largecode.ll | 10 |
2 files changed, 21 insertions, 5 deletions
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index c71c6ec..9badfc8 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -426,3 +426,19 @@ while.end: ; preds = %if.then.i256 return: ; preds = %entry ret i64 -131 } + +; The tail call to a varargs function sets %AL. +; uitofp expands to an FCMOV instruction which splits the basic block. +; Make sure the live range of %AL isn't split. +@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32 +define void @pr13188(i64* nocapture %this) uwtable ssp address_safety align 2 { +entry: + %x7 = load i64* %this, align 8 + %sub = add i64 %x7, -1 + %conv = uitofp i64 %sub to float + %div = fmul float %conv, 5.000000e-01 + %conv2 = fpext float %div to double + tail call void (...)* @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2) + ret void +} +declare void @_Z6PrintFz(...) diff --git a/test/CodeGen/X86/tailcall-largecode.ll b/test/CodeGen/X86/tailcall-largecode.ll index c3f4278..e9b8721 100644 --- a/test/CodeGen/X86/tailcall-largecode.ll +++ b/test/CodeGen/X86/tailcall-largecode.ll @@ -49,6 +49,11 @@ define fastcc i32 @direct_manyargs() { ; CHECK: pushq ; Pass the stack argument. ; CHECK: movl $7, 16(%rsp) +; This is the large code model, so &manyargs_callee may not fit into +; the jmp instruction. Put it into a register which won't be clobbered +; while restoring callee-saved registers and won't be used for passing +; arguments. +; CHECK: movabsq $manyargs_callee, %rax ; Pass the register arguments, in the right registers. ; CHECK: movl $1, %edi ; CHECK: movl $2, %esi @@ -56,11 +61,6 @@ define fastcc i32 @direct_manyargs() { ; CHECK: movl $4, %ecx ; CHECK: movl $5, %r8d ; CHECK: movl $6, %r9d -; This is the large code model, so &manyargs_callee may not fit into -; the jmp instruction. Put it into R11, which won't be clobbered -; while restoring callee-saved registers and won't be used for passing -; arguments. -; CHECK: movabsq $manyargs_callee, %rax ; Adjust the stack to "return". ; CHECK: popq ; And tail-call to the target. |