diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 19:58:23 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 19:58:23 +0000 |
| commit | d597263b9442923bacc24f26a8510fb69f992864 (patch) | |
| tree | 701478fef64be3c439f5d1cd02ef6054003fe009 /test/CodeGen | |
| parent | 6804971dcfbba1dcf7b0f8335588ba2ab6b0f073 (diff) | |
| download | external_llvm-d597263b9442923bacc24f26a8510fb69f992864.zip external_llvm-d597263b9442923bacc24f26a8510fb69f992864.tar.gz external_llvm-d597263b9442923bacc24f26a8510fb69f992864.tar.bz2 | |
[mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/Mips/dsp-patterns.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll index c2aeab5..eeb7140 100644 --- a/test/CodeGen/Mips/dsp-patterns.ll +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -203,3 +203,59 @@ entry: %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 ret { i32 } %.fca.0.insert } + +; Check that shift node is expanded if splat element size is not 16-bit. +; +; R1: test_vector_splat_imm_v2q15: +; R1-NOT: shll.ph + +define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %shl = shl <2 x i16> %0, <i16 0, i16 2> + %1 = bitcast <2 x i16> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if splat element size is not 8-bit. +; +; R1: test_vector_splat_imm_v4i8: +; R1-NOT: shll.qb + +define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %shl = shl <4 x i8> %0, <i8 0, i8 2, i8 0, i8 2> + %1 = bitcast <4 x i8> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field. +; +; R1: test_shift_amount_v2q15: +; R1-NOT: shll.ph + +define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %shl = shl <2 x i16> %0, <i16 16, i16 16> + %1 = bitcast <2 x i16> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field. +; +; R1: test_shift_amount_v4i8: +; R1-NOT: shll.qb + +define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %shl = shl <4 x i8> %0, <i8 8, i8 8, i8 8, i8 8> + %1 = bitcast <4 x i8> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} |