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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:32:10 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:32:10 +0000 |
commit | d950941e138455ebcd7a5f55805dcb977892e3e3 (patch) | |
tree | f9732e3dd797f8f76f0c886f57f295daeb1f1a92 /test/CodeGen | |
parent | 4ea480499c40cd7e28bf35cacda33ccbab2aab07 (diff) | |
download | external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.zip external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.tar.gz external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.tar.bz2 |
Analog Devices Blackfin back-end.
Generate code for the Blackfin family of DSPs from Analog Devices:
http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
We aim to be compatible with the exsisting GNU toolchain found at:
http://blackfin.uclinux.org/gf/project/toolchain
The back-end is experimental.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
47 files changed, 1238 insertions, 0 deletions
diff --git a/test/CodeGen/Blackfin/add-overflow.ll b/test/CodeGen/Blackfin/add-overflow.ll new file mode 100644 index 0000000..de80783 --- /dev/null +++ b/test/CodeGen/Blackfin/add-overflow.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + + type { i24, i1 } ; type %0 + +define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind { +entry: + %t = call %0 @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2) ; <%0> [#uses=1] + %obit = extractvalue %0 %t, 1 ; <i1> [#uses=1] + br i1 %obit, label %carry, label %normal + +normal: ; preds = %entry + ret i1 true + +carry: ; preds = %entry + ret i1 false +} + +declare %0 @llvm.uadd.with.overflow.i24(i24, i24) nounwind diff --git a/test/CodeGen/Blackfin/add.ll b/test/CodeGen/Blackfin/add.ll new file mode 100644 index 0000000..267f309 --- /dev/null +++ b/test/CodeGen/Blackfin/add.ll @@ -0,0 +1,5 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +define i32 @add(i32 %A, i32 %B) { + %R = add i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} diff --git a/test/CodeGen/Blackfin/addsub-i128.ll b/test/CodeGen/Blackfin/addsub-i128.ll new file mode 100644 index 0000000..8dd04d8 --- /dev/null +++ b/test/CodeGen/Blackfin/addsub-i128.ll @@ -0,0 +1,42 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +; XFAIL: * +; Assertion failed: (isUsed(Reg) && "Using an undefined register!"), +; function forward, file RegisterScavenging.cpp, line 182. + +define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { +entry: + %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1] + %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1] + %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1] + %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1] + %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1] + %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] + %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1] + %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1] + %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2] + %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1] + store i64 %tmp1617, i64* %RL + %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1] + %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1] + store i64 %tmp2122, i64* %RH + ret void +} + +define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { +entry: + %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1] + %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1] + %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1] + %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1] + %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1] + %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] + %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1] + %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1] + %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2] + %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1] + store i64 %tmp1617, i64* %RL + %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1] + %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1] + store i64 %tmp2122, i64* %RH + ret void +} diff --git a/test/CodeGen/Blackfin/basic-i1.ll b/test/CodeGen/Blackfin/basic-i1.ll new file mode 100644 index 0000000..1c0c72a --- /dev/null +++ b/test/CodeGen/Blackfin/basic-i1.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=bfin > %t + +define i1 @add(i1 %A, i1 %B) { + %R = add i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @sub(i1 %A, i1 %B) { + %R = sub i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @mul(i1 %A, i1 %B) { + %R = mul i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @sdiv(i1 %A, i1 %B) { + %R = sdiv i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @udiv(i1 %A, i1 %B) { + %R = udiv i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @srem(i1 %A, i1 %B) { + %R = srem i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @urem(i1 %A, i1 %B) { + %R = urem i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @and(i1 %A, i1 %B) { + %R = and i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @or(i1 %A, i1 %B) { + %R = or i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} + +define i1 @xor(i1 %A, i1 %B) { + %R = xor i1 %A, %B ; <i1> [#uses=1] + ret i1 %R +} diff --git a/test/CodeGen/Blackfin/basic-i16.ll b/test/CodeGen/Blackfin/basic-i16.ll new file mode 100644 index 0000000..d850631 --- /dev/null +++ b/test/CodeGen/Blackfin/basic-i16.ll @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llc -march=bfin + +define i16 @add(i16 %A, i16 %B) { + %R = add i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @sub(i16 %A, i16 %B) { + %R = sub i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @mul(i16 %A, i16 %B) { + %R = mul i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @sdiv(i16 %A, i16 %B) { + %R = sdiv i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @udiv(i16 %A, i16 %B) { + %R = udiv i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @srem(i16 %A, i16 %B) { + %R = srem i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @urem(i16 %A, i16 %B) { + %R = urem i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} diff --git a/test/CodeGen/Blackfin/basic-i32.ll b/test/CodeGen/Blackfin/basic-i32.ll new file mode 100644 index 0000000..3a9377c --- /dev/null +++ b/test/CodeGen/Blackfin/basic-i32.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +define i32 @add(i32 %A, i32 %B) { + %R = add i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @sub(i32 %A, i32 %B) { + %R = sub i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @mul(i32 %A, i32 %B) { + %R = mul i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @sdiv(i32 %A, i32 %B) { + %R = sdiv i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @udiv(i32 %A, i32 %B) { + %R = udiv i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @srem(i32 %A, i32 %B) { + %R = srem i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @urem(i32 %A, i32 %B) { + %R = urem i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @and(i32 %A, i32 %B) { + %R = and i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @or(i32 %A, i32 %B) { + %R = or i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @xor(i32 %A, i32 %B) { + %R = xor i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} diff --git a/test/CodeGen/Blackfin/basic-i64.ll b/test/CodeGen/Blackfin/basic-i64.ll new file mode 100644 index 0000000..32dfc1c --- /dev/null +++ b/test/CodeGen/Blackfin/basic-i64.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +define i64 @add(i64 %A, i64 %B) { + %R = add i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @sub(i64 %A, i64 %B) { + %R = sub i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @mul(i64 %A, i64 %B) { + %R = mul i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @sdiv(i64 %A, i64 %B) { + %R = sdiv i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @udiv(i64 %A, i64 %B) { + %R = udiv i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @srem(i64 %A, i64 %B) { + %R = srem i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @urem(i64 %A, i64 %B) { + %R = urem i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @and(i64 %A, i64 %B) { + %R = and i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @or(i64 %A, i64 %B) { + %R = or i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} + +define i64 @xor(i64 %A, i64 %B) { + %R = xor i64 %A, %B ; <i64> [#uses=1] + ret i64 %R +} diff --git a/test/CodeGen/Blackfin/basic-i8.ll b/test/CodeGen/Blackfin/basic-i8.ll new file mode 100644 index 0000000..7338d46 --- /dev/null +++ b/test/CodeGen/Blackfin/basic-i8.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=bfin + +define i8 @add(i8 %A, i8 %B) { + %R = add i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @sub(i8 %A, i8 %B) { + %R = sub i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @mul(i8 %A, i8 %B) { + %R = mul i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @sdiv(i8 %A, i8 %B) { + %R = sdiv i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @udiv(i8 %A, i8 %B) { + %R = udiv i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @srem(i8 %A, i8 %B) { + %R = srem i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @urem(i8 %A, i8 %B) { + %R = urem i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @and(i8 %A, i8 %B) { + %R = and i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @or(i8 %A, i8 %B) { + %R = or i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} + +define i8 @xor(i8 %A, i8 %B) { + %R = xor i8 %A, %B ; <i8> [#uses=1] + ret i8 %R +} diff --git a/test/CodeGen/Blackfin/basictest.ll b/test/CodeGen/Blackfin/basictest.ll new file mode 100644 index 0000000..09a389d --- /dev/null +++ b/test/CodeGen/Blackfin/basictest.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +define void @void(i32, i32) { + add i32 0, 0 ; <i32>:3 [#uses=2] + sub i32 0, 4 ; <i32>:4 [#uses=2] + br label %5 + +; <label>:5 ; preds = %5, %2 + add i32 %0, %1 ; <i32>:6 [#uses=2] + sub i32 %6, %4 ; <i32>:7 [#uses=1] + icmp sle i32 %7, %3 ; <i1>:8 [#uses=1] + br i1 %8, label %9, label %5 + +; <label>:9 ; preds = %5 + add i32 %0, %1 ; <i32>:10 [#uses=0] + sub i32 %6, %4 ; <i32>:11 [#uses=1] + icmp sle i32 %11, %3 ; <i1>:12 [#uses=0] + ret void +} diff --git a/test/CodeGen/Blackfin/burg.ll b/test/CodeGen/Blackfin/burg.ll new file mode 100644 index 0000000..fb5f74b --- /dev/null +++ b/test/CodeGen/Blackfin/burg.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + + %IntList = type %struct.intlist* + %ReadFn = type i32 ()* + %YYSTYPE = type { %IntList } + %struct.intlist = type { i32, %IntList } +@yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] + +define i32 @yyparse() { +bb0: + %reg254 = load i16* null ; <i16> [#uses=1] + %reg254-idxcast = sext i16 %reg254 to i64 ; <i64> [#uses=1] + %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; <i64> [#uses=1] + %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; <i64> [#uses=1] + %reg261.idx1 = getelementptr %YYSTYPE* null, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1] + %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1] + store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) + unreachable +} diff --git a/test/CodeGen/Blackfin/cmp-small-imm.ll b/test/CodeGen/Blackfin/cmp-small-imm.ll new file mode 100644 index 0000000..7d87cb0 --- /dev/null +++ b/test/CodeGen/Blackfin/cmp-small-imm.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin > %t +; XFAIL: * +; Assertion failed: (isUsed(Reg) && "Using an undefined register!") +; function forward, file RegisterScavenging.cpp, line 259. + +define i1 @cmp3(i32 %A) { + %R = icmp uge i32 %A, 2 + ret i1 %R +} diff --git a/test/CodeGen/Blackfin/cmp64.ll b/test/CodeGen/Blackfin/cmp64.ll new file mode 100644 index 0000000..c5c5f7e --- /dev/null +++ b/test/CodeGen/Blackfin/cmp64.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=bfin + +; This test tries to use a JustCC register as a data operand for MOVEcc. It +; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to +; D. The proper solution would be to restrict the virtual register to D only. + +define i32 @main() { +entry: + br label %loopentry + +loopentry: + %done = icmp sle i64 undef, 5 + br i1 %done, label %loopentry, label %exit.1 + +exit.1: + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/ct32.ll b/test/CodeGen/Blackfin/ct32.ll new file mode 100644 index 0000000..ab5b12f --- /dev/null +++ b/test/CodeGen/Blackfin/ct32.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i32 @llvm.ctlz.i32(i32) +declare i32 @llvm.cttz.i32(i32) +declare i32 @llvm.ctpop.i32(i32) + +define i32 @ctlztest(i32 %B) { + %b = call i32 @llvm.ctlz.i32( i32 %B ) + ret i32 %b; +} + +define i32 @cttztest(i32 %B) { + %b = call i32 @llvm.cttz.i32( i32 %B ) + ret i32 %b; +} + +define i32 @ctpoptest(i32 %B) { + %b = call i32 @llvm.ctpop.i32( i32 %B ) + ret i32 %b; +} diff --git a/test/CodeGen/Blackfin/ct64.ll b/test/CodeGen/Blackfin/ct64.ll new file mode 100644 index 0000000..43cde5e --- /dev/null +++ b/test/CodeGen/Blackfin/ct64.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i64 @llvm.ctlz.i64(i64) +declare i64 @llvm.cttz.i64(i64) +declare i64 @llvm.ctpop.i64(i64) + +define i64 @ctlztest(i64 %B) { + %b = call i64 @llvm.ctlz.i64( i64 %B ) + ret i64 %b; +} + +define i64 @cttztest(i64 %B) { + %b = call i64 @llvm.cttz.i64( i64 %B ) + ret i64 %b; +} + +define i64 @ctpoptest(i64 %B) { + %b = call i64 @llvm.ctpop.i64( i64 %B ) + ret i64 %b; +} diff --git a/test/CodeGen/Blackfin/ctlz16.ll b/test/CodeGen/Blackfin/ctlz16.ll new file mode 100644 index 0000000..039ffbd --- /dev/null +++ b/test/CodeGen/Blackfin/ctlz16.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i16 @llvm.ctlz.i16(i16) + +define i16 @ctlztest(i16 %B) { + %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} +define i16 @ctlztest_z(i16 zeroext %B) { + %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + +define i16 @ctlztest_s(i16 signext %B) { + %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + diff --git a/test/CodeGen/Blackfin/ctlz64.ll b/test/CodeGen/Blackfin/ctlz64.ll new file mode 100644 index 0000000..276b1d5 --- /dev/null +++ b/test/CodeGen/Blackfin/ctlz64.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + +@.str = external constant [14 x i8] ; <[14 x i8]*> [#uses=1] + +define i32 @main(i64 %arg) nounwind { +entry: + %tmp47 = tail call i64 @llvm.cttz.i64(i64 %arg) ; <i64> [#uses=1] + %tmp48 = trunc i64 %tmp47 to i32 ; <i32> [#uses=1] + %tmp40 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 0, i32 %tmp48, i32 0) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @printf(i8* noalias, ...) nounwind + +declare i64 @llvm.cttz.i64(i64) nounwind readnone diff --git a/test/CodeGen/Blackfin/ctpop16.ll b/test/CodeGen/Blackfin/ctpop16.ll new file mode 100644 index 0000000..cb06aa2 --- /dev/null +++ b/test/CodeGen/Blackfin/ctpop16.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i16 @llvm.ctpop.i16(i16) + +define i16 @ctpoptest(i16 %B) { + %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} +define i16 @ctpoptest_z(i16 zeroext %B) { + %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + +define i16 @ctpoptest_s(i16 signext %B) { + %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + diff --git a/test/CodeGen/Blackfin/cttz16.ll b/test/CodeGen/Blackfin/cttz16.ll new file mode 100644 index 0000000..a76cd36 --- /dev/null +++ b/test/CodeGen/Blackfin/cttz16.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i16 @llvm.cttz.i16(i16) + +define i16 @cttztest(i16 %B) { + %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} +define i16 @cttztest_z(i16 zeroext %B) { + %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + +define i16 @cttztest_s(i16 signext %B) { + %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1] + ret i16 %b; +} + diff --git a/test/CodeGen/Blackfin/cycles.ll b/test/CodeGen/Blackfin/cycles.ll new file mode 100644 index 0000000..042cb57 --- /dev/null +++ b/test/CodeGen/Blackfin/cycles.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=bfin | grep cycles +; XFAIL: * +; ExpandIntegerResult #0: 0x181a60c: i64,ch = ReadCycleCounter 0x1104b08 +; Do not know how to expand the result of this operator! + +declare i64 @llvm.readcyclecounter() + +define i64 @foo() { + %tmp.1 = call i64 @llvm.readcyclecounter() + ret i64 %tmp.1 +} diff --git a/test/CodeGen/Blackfin/dg.exp b/test/CodeGen/Blackfin/dg.exp new file mode 100644 index 0000000..5fdbe5f --- /dev/null +++ b/test/CodeGen/Blackfin/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target Blackfin] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} diff --git a/test/CodeGen/Blackfin/double-cast.ll b/test/CodeGen/Blackfin/double-cast.ll new file mode 100644 index 0000000..774615f --- /dev/null +++ b/test/CodeGen/Blackfin/double-cast.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=bfin + +declare i32 @printf(i8*, ...) + +define i32 @main() { + %1 = call i32 (i8*, ...)* @printf(i8* undef, double undef) + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/frameindex.ll b/test/CodeGen/Blackfin/frameindex.ll new file mode 100644 index 0000000..34ca3eb --- /dev/null +++ b/test/CodeGen/Blackfin/frameindex.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +declare i32 @SIM(i8*, i8*, i32, i32, i32, [256 x i32]*, i32, i32, i32) + +define void @foo() { +bb0: + %V = alloca [256 x i32], i32 256 ; <[256 x i32]*> [#uses=1] + %0 = call i32 @SIM(i8* null, i8* null, i32 0, i32 0, i32 0, [256 x i32]* %V, i32 0, i32 0, i32 2) ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/Blackfin/i17mem.ll b/test/CodeGen/Blackfin/i17mem.ll new file mode 100644 index 0000000..6a3b394 --- /dev/null +++ b/test/CodeGen/Blackfin/i17mem.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i17_l = external global i17 ; <i17*> [#uses=1] +@i17_s = external global i17 ; <i17*> [#uses=1] + +define void @i17_ls() nounwind { + %tmp = load i17* @i17_l ; <i17> [#uses=1] + store i17 %tmp, i17* @i17_s + ret void +} diff --git a/test/CodeGen/Blackfin/i1mem.ll b/test/CodeGen/Blackfin/i1mem.ll new file mode 100644 index 0000000..97bc035 --- /dev/null +++ b/test/CodeGen/Blackfin/i1mem.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i1_l = external global i1 ; <i1*> [#uses=1] +@i1_s = external global i1 ; <i1*> [#uses=1] + +define void @i1_ls() nounwind { + %tmp = load i1* @i1_l ; <i1> [#uses=1] + store i1 %tmp, i1* @i1_s + ret void +} diff --git a/test/CodeGen/Blackfin/i1ops.ll b/test/CodeGen/Blackfin/i1ops.ll new file mode 100644 index 0000000..0bbd198 --- /dev/null +++ b/test/CodeGen/Blackfin/i1ops.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +define i32 @adj(i32 %d.1, i32 %ct.1) { +entry: + %tmp.22.not = trunc i32 %ct.1 to i1 ; <i1> [#uses=1] + %tmp.221 = xor i1 %tmp.22.not, true ; <i1> [#uses=1] + %tmp.26 = or i1 false, %tmp.221 ; <i1> [#uses=1] + %tmp.27 = zext i1 %tmp.26 to i32 ; <i32> [#uses=1] + ret i32 %tmp.27 +} diff --git a/test/CodeGen/Blackfin/i216mem.ll b/test/CodeGen/Blackfin/i216mem.ll new file mode 100644 index 0000000..085dc15 --- /dev/null +++ b/test/CodeGen/Blackfin/i216mem.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i216_l = external global i216 ; <i216*> [#uses=1] +@i216_s = external global i216 ; <i216*> [#uses=1] + +define void @i216_ls() nounwind { + %tmp = load i216* @i216_l ; <i216> [#uses=1] + store i216 %tmp, i216* @i216_s + ret void +} diff --git a/test/CodeGen/Blackfin/i248mem.ll b/test/CodeGen/Blackfin/i248mem.ll new file mode 100644 index 0000000..7dde2a1 --- /dev/null +++ b/test/CodeGen/Blackfin/i248mem.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin +@i248_l = external global i248 ; <i248*> [#uses=1] +@i248_s = external global i248 ; <i248*> [#uses=1] + +define void @i248_ls() nounwind { + %tmp = load i248* @i248_l ; <i248> [#uses=1] + store i248 %tmp, i248* @i248_s + ret void +} diff --git a/test/CodeGen/Blackfin/i256mem.ll b/test/CodeGen/Blackfin/i256mem.ll new file mode 100644 index 0000000..6a3b394 --- /dev/null +++ b/test/CodeGen/Blackfin/i256mem.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i17_l = external global i17 ; <i17*> [#uses=1] +@i17_s = external global i17 ; <i17*> [#uses=1] + +define void @i17_ls() nounwind { + %tmp = load i17* @i17_l ; <i17> [#uses=1] + store i17 %tmp, i17* @i17_s + ret void +} diff --git a/test/CodeGen/Blackfin/i256param.ll b/test/CodeGen/Blackfin/i256param.ll new file mode 100644 index 0000000..85a74fa --- /dev/null +++ b/test/CodeGen/Blackfin/i256param.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i256_s = external global i256 ; <i256*> [#uses=1] + +define void @i256_ls(i256 %x) nounwind { + store i256 %x, i256* @i256_s + ret void +} diff --git a/test/CodeGen/Blackfin/i56param.ll b/test/CodeGen/Blackfin/i56param.ll new file mode 100644 index 0000000..a03c182 --- /dev/null +++ b/test/CodeGen/Blackfin/i56param.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@i56_l = external global i56 ; <i56*> [#uses=1] +@i56_s = external global i56 ; <i56*> [#uses=1] + +define void @i56_ls(i56 %x) nounwind { + store i56 %x, i56* @i56_s + ret void +} diff --git a/test/CodeGen/Blackfin/i8mem.ll b/test/CodeGen/Blackfin/i8mem.ll new file mode 100644 index 0000000..967a86f --- /dev/null +++ b/test/CodeGen/Blackfin/i8mem.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=bfin + +@i8_l = external global i8 ; <i8*> [#uses=1] +@i8_s = external global i8 ; <i8*> [#uses=1] + +define void @i8_ls() nounwind { + %tmp = load i8* @i8_l ; <i8> [#uses=1] + store i8 %tmp, i8* @i8_s + ret void +} diff --git a/test/CodeGen/Blackfin/int-setcc.ll b/test/CodeGen/Blackfin/int-setcc.ll new file mode 100644 index 0000000..e1f822b --- /dev/null +++ b/test/CodeGen/Blackfin/int-setcc.ll @@ -0,0 +1,80 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + +define fastcc void @Evaluate() { +entry: + br i1 false, label %cond_false186, label %cond_true + +cond_true: ; preds = %entry + ret void + +cond_false186: ; preds = %entry + br i1 false, label %cond_true293, label %bb203 + +bb203: ; preds = %cond_false186 + ret void + +cond_true293: ; preds = %cond_false186 + br i1 false, label %cond_true298, label %cond_next317 + +cond_true298: ; preds = %cond_true293 + br i1 false, label %cond_next518, label %cond_true397.preheader + +cond_next317: ; preds = %cond_true293 + ret void + +cond_true397.preheader: ; preds = %cond_true298 + ret void + +cond_next518: ; preds = %cond_true298 + br i1 false, label %bb1069, label %cond_true522 + +cond_true522: ; preds = %cond_next518 + ret void + +bb1069: ; preds = %cond_next518 + br i1 false, label %cond_next1131, label %bb1096 + +bb1096: ; preds = %bb1069 + ret void + +cond_next1131: ; preds = %bb1069 + br i1 false, label %cond_next1207, label %cond_true1150 + +cond_true1150: ; preds = %cond_next1131 + ret void + +cond_next1207: ; preds = %cond_next1131 + br i1 false, label %cond_next1219, label %cond_true1211 + +cond_true1211: ; preds = %cond_next1207 + ret void + +cond_next1219: ; preds = %cond_next1207 + br i1 false, label %cond_true1223, label %cond_next1283 + +cond_true1223: ; preds = %cond_next1219 + br i1 false, label %cond_true1254, label %cond_true1264 + +cond_true1254: ; preds = %cond_true1223 + br i1 false, label %bb1567, label %cond_true1369.preheader + +cond_true1264: ; preds = %cond_true1223 + ret void + +cond_next1283: ; preds = %cond_next1219 + ret void + +cond_true1369.preheader: ; preds = %cond_true1254 + ret void + +bb1567: ; preds = %cond_true1254 + %tmp1605 = load i8* null ; <i8> [#uses=1] + %tmp1606 = icmp eq i8 %tmp1605, 0 ; <i1> [#uses=1] + br i1 %tmp1606, label %cond_next1637, label %cond_true1607 + +cond_true1607: ; preds = %bb1567 + ret void + +cond_next1637: ; preds = %bb1567 + ret void +} diff --git a/test/CodeGen/Blackfin/invalid-apint.ll b/test/CodeGen/Blackfin/invalid-apint.ll new file mode 100644 index 0000000..bc3bbb3 --- /dev/null +++ b/test/CodeGen/Blackfin/invalid-apint.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=bfin + +; Assertion failed: (width < BitWidth && "Invalid APInt Truncate request"), +; function trunc, file APInt.cpp, line 956. + +@str2 = external global [29 x i8] + +define void @printArgsNoRet(i32 %a1, float %a2, i8 %a3, double %a4, i8* %a5, i32 %a6, float %a7, i8 %a8, double %a9, i8* %a10, i32 %a11, float %a12, i8 %a13, double %a14, i8* %a15) { +entry: + %tmp17 = sext i8 %a13 to i32 + %tmp23 = call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @str2, i32 0, i64 0), i32 %a11, double 0.000000e+00, i32 %tmp17, double %a14, i32 0) + ret void +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Blackfin/jumptable.ll b/test/CodeGen/Blackfin/jumptable.ll new file mode 100644 index 0000000..62b5831 --- /dev/null +++ b/test/CodeGen/Blackfin/jumptable.ll @@ -0,0 +1,53 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs | FileCheck %s + +; CHECK: .section .rodata +; CHECK: JTI1_0: +; CHECK: .long .BB1_1 + +define i32 @oper(i32 %op, i32 %A, i32 %B) { +entry: + switch i32 %op, label %bbx [ + i32 1 , label %bb1 + i32 2 , label %bb2 + i32 3 , label %bb3 + i32 4 , label %bb4 + i32 5 , label %bb5 + i32 6 , label %bb6 + i32 7 , label %bb7 + i32 8 , label %bb8 + i32 9 , label %bb9 + i32 10, label %bb10 + ] +bb1: + %R1 = add i32 %A, %B ; <i32> [#uses=1] + ret i32 %R1 +bb2: + %R2 = sub i32 %A, %B ; <i32> [#uses=1] + ret i32 %R2 +bb3: + %R3 = mul i32 %A, %B ; <i32> [#uses=1] + ret i32 %R3 +bb4: + %R4 = sdiv i32 %A, %B ; <i32> [#uses=1] + ret i32 %R4 +bb5: + %R5 = udiv i32 %A, %B ; <i32> [#uses=1] + ret i32 %R5 +bb6: + %R6 = srem i32 %A, %B ; <i32> [#uses=1] + ret i32 %R6 +bb7: + %R7 = urem i32 %A, %B ; <i32> [#uses=1] + ret i32 %R7 +bb8: + %R8 = and i32 %A, %B ; <i32> [#uses=1] + ret i32 %R8 +bb9: + %R9 = or i32 %A, %B ; <i32> [#uses=1] + ret i32 %R9 +bb10: + %R10 = xor i32 %A, %B ; <i32> [#uses=1] + ret i32 %R10 +bbx: + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/large-switch.ll b/test/CodeGen/Blackfin/large-switch.ll new file mode 100644 index 0000000..42aa4cd --- /dev/null +++ b/test/CodeGen/Blackfin/large-switch.ll @@ -0,0 +1,187 @@ +; RUN: llvm-as < %s | llc -march=bfin + +; The switch expansion uses a dynamic shl, and it produces a jumptable + +define void @athlon_fp_unit_ready_cost() { +entry: + switch i32 0, label %UnifiedReturnBlock [ + i32 -1, label %bb2063 + i32 19, label %bb2035 + i32 20, label %bb2035 + i32 21, label %bb2035 + i32 23, label %bb2035 + i32 24, label %bb2035 + i32 27, label %bb2035 + i32 32, label %bb2035 + i32 33, label %bb1994 + i32 35, label %bb2035 + i32 36, label %bb1994 + i32 90, label %bb1948 + i32 94, label %bb1948 + i32 95, label %bb1948 + i32 133, label %bb1419 + i32 135, label %bb1238 + i32 136, label %bb1238 + i32 137, label %bb1238 + i32 138, label %bb1238 + i32 139, label %bb1201 + i32 140, label %bb1201 + i32 141, label %bb1154 + i32 142, label %bb1126 + i32 144, label %bb1201 + i32 145, label %bb1126 + i32 146, label %bb1201 + i32 147, label %bb1126 + i32 148, label %bb1201 + i32 149, label %bb1126 + i32 150, label %bb1201 + i32 151, label %bb1126 + i32 152, label %bb1096 + i32 153, label %bb1096 + i32 154, label %bb1096 + i32 157, label %bb1096 + i32 158, label %bb1096 + i32 159, label %bb1096 + i32 162, label %bb1096 + i32 163, label %bb1096 + i32 164, label %bb1096 + i32 167, label %bb1201 + i32 168, label %bb1201 + i32 170, label %bb1201 + i32 171, label %bb1201 + i32 173, label %bb1201 + i32 174, label %bb1201 + i32 176, label %bb1201 + i32 177, label %bb1201 + i32 179, label %bb993 + i32 180, label %bb993 + i32 181, label %bb993 + i32 182, label %bb993 + i32 183, label %bb993 + i32 184, label %bb993 + i32 365, label %bb1126 + i32 366, label %bb1126 + i32 367, label %bb1126 + i32 368, label %bb1126 + i32 369, label %bb1126 + i32 370, label %bb1126 + i32 371, label %bb1126 + i32 372, label %bb1126 + i32 373, label %bb1126 + i32 384, label %bb1126 + i32 385, label %bb1126 + i32 386, label %bb1126 + i32 387, label %bb1126 + i32 388, label %bb1126 + i32 389, label %bb1126 + i32 390, label %bb1126 + i32 391, label %bb1126 + i32 392, label %bb1126 + i32 525, label %bb919 + i32 526, label %bb839 + i32 528, label %bb919 + i32 529, label %bb839 + i32 532, label %cond_next6.i97 + i32 533, label %cond_next6.i81 + i32 534, label %bb495 + i32 536, label %cond_next6.i81 + i32 537, label %cond_next6.i81 + i32 538, label %bb396 + i32 539, label %bb288 + i32 541, label %bb396 + i32 542, label %bb396 + i32 543, label %bb396 + i32 544, label %bb396 + i32 545, label %bb189 + i32 546, label %cond_next6.i + i32 547, label %bb189 + i32 548, label %cond_next6.i + i32 549, label %bb189 + i32 550, label %cond_next6.i + i32 551, label %bb189 + i32 552, label %cond_next6.i + i32 553, label %bb189 + i32 554, label %cond_next6.i + i32 555, label %bb189 + i32 556, label %cond_next6.i + i32 557, label %bb189 + i32 558, label %cond_next6.i + i32 618, label %bb40 + i32 619, label %bb18 + i32 620, label %bb40 + i32 621, label %bb10 + i32 622, label %bb10 + ] + +bb10: + ret void + +bb18: + ret void + +bb40: + ret void + +cond_next6.i: + ret void + +bb189: + ret void + +bb288: + ret void + +bb396: + ret void + +bb495: + ret void + +cond_next6.i81: + ret void + +cond_next6.i97: + ret void + +bb839: + ret void + +bb919: + ret void + +bb993: + ret void + +bb1096: + ret void + +bb1126: + ret void + +bb1154: + ret void + +bb1201: + ret void + +bb1238: + ret void + +bb1419: + ret void + +bb1948: + ret void + +bb1994: + ret void + +bb2035: + ret void + +bb2063: + ret void + +UnifiedReturnBlock: + ret void +} diff --git a/test/CodeGen/Blackfin/load-i16.ll b/test/CodeGen/Blackfin/load-i16.ll new file mode 100644 index 0000000..853b662 --- /dev/null +++ b/test/CodeGen/Blackfin/load-i16.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + +; This somewhat contrived function heavily exercises register classes +; It can trick -join-cross-class-copies into making illegal joins + +define void @f(i16** nocapture %p) nounwind readonly { +entry: + %tmp1 = load i16** %p ; <i16*> [#uses=1] + %tmp2 = load i16* %tmp1 ; <i16> [#uses=1] + %ptr = getelementptr i16* %tmp1, i16 %tmp2 + store i16 %tmp2, i16* %ptr + ret void +} diff --git a/test/CodeGen/Blackfin/logic-i16.ll b/test/CodeGen/Blackfin/logic-i16.ll new file mode 100644 index 0000000..fba0afb --- /dev/null +++ b/test/CodeGen/Blackfin/logic-i16.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=bfin + +define i16 @and(i16 %A, i16 %B) { + %R = and i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @or(i16 %A, i16 %B) { + %R = or i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} + +define i16 @xor(i16 %A, i16 %B) { + %R = xor i16 %A, %B ; <i16> [#uses=1] + ret i16 %R +} diff --git a/test/CodeGen/Blackfin/many-args.ll b/test/CodeGen/Blackfin/many-args.ll new file mode 100644 index 0000000..3160d6c --- /dev/null +++ b/test/CodeGen/Blackfin/many-args.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs + + type { i32, float, float, float, float, float, float, float, float, float, float } ; type %0 + %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float } + +define i32 @main(i32 %argc.1, i8** %argv.1) { +entry: + %tmp.218 = load float* null ; <float> [#uses=1] + %tmp.219 = getelementptr %0* null, i64 0, i32 6 ; <float*> [#uses=1] + %tmp.220 = load float* %tmp.219 ; <float> [#uses=1] + %tmp.221 = getelementptr %0* null, i64 0, i32 7 ; <float*> [#uses=1] + %tmp.222 = load float* %tmp.221 ; <float> [#uses=1] + %tmp.223 = getelementptr %0* null, i64 0, i32 8 ; <float*> [#uses=1] + %tmp.224 = load float* %tmp.223 ; <float> [#uses=1] + %tmp.225 = getelementptr %0* null, i64 0, i32 9 ; <float*> [#uses=1] + %tmp.226 = load float* %tmp.225 ; <float> [#uses=1] + %tmp.227 = getelementptr %0* null, i64 0, i32 10 ; <float*> [#uses=1] + %tmp.228 = load float* %tmp.227 ; <float> [#uses=1] + call void @place_and_route(i32 0, i32 0, float 0.000000e+00, i32 0, i32 0, i8* null, i32 0, i32 0, i8* null, i8* null, i8* null, i8* null, i32 0, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i32 0, i32 0, i32 0, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i32 0, i32 0, i16 0, i16 0, i16 0, float 0.000000e+00, float 0.000000e+00, %struct..s_segment_inf* null, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %tmp.218, float %tmp.220, float %tmp.222, float %tmp.224, float %tmp.226, float %tmp.228) + ret i32 0 +} + +declare void @place_and_route(i32, i32, float, i32, i32, i8*, i32, i32, i8*, i8*, i8*, i8*, i32, i32, i32, float, float, float, float, float, float, float, float, float, i32, i32, i32, i32, i32, float, float, float, i32, i32, i16, i16, i16, float, float, %struct..s_segment_inf*, i32, float, float, float, float, float, float, float, float, float, float) diff --git a/test/CodeGen/Blackfin/mulhu.ll b/test/CodeGen/Blackfin/mulhu.ll new file mode 100644 index 0000000..91be4502 --- /dev/null +++ b/test/CodeGen/Blackfin/mulhu.ll @@ -0,0 +1,106 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + + %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } + %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] } + %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] } + %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 } + %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* } + %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] } + %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* } + %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack } + %struct.cost_pair = type { %struct.iv_cand*, i32, %struct.bitmap_head_def* } + %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] } + %struct.def_operand_ptr = type { %struct.tree_node** } + %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] } + %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 } + %struct.edge_def_insns = type { %struct.rtx_def* } + %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 } + %struct.eh_status = type opaque + %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } + %struct.et_node = type opaque + %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } + %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i1, i1, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 } + %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 } + %struct.initial_value_struct = type opaque + %struct.iv = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i1, i1, i32 } + %struct.iv_cand = type { i32, i1, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.iv*, i32 } + %struct.iv_use = type { i32, i32, %struct.iv*, %struct.tree_node*, %struct.tree_node**, %struct.bitmap_head_def*, i32, %struct.cost_pair*, %struct.iv_cand* } + %struct.ivopts_data = type { %struct.loop*, %struct.htab*, i32, %struct.version_info*, %struct.bitmap_head_def*, i32, %struct.varray_head_tag*, %struct.varray_head_tag*, %struct.bitmap_head_def*, i1 } + %struct.lang_decl = type opaque + %struct.language_function = type opaque + %struct.location_t = type { i8*, i32 } + %struct.loop = type { i32, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.lpt_decision, i32, i32, %struct.edge_def**, i32, %struct.basic_block_def*, %struct.basic_block_def*, i32, %struct.edge_def**, i32, %struct.edge_def**, i32, %struct.simple_bitmap_def*, i32, %struct.loop**, i32, %struct.loop*, %struct.loop*, %struct.loop*, %struct.loop*, i32, i8*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound*, %struct.edge_def*, i1 } + %struct.lpt_decision = type { i32, i32 } + %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 } + %struct.nb_iter_bound = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound* } + %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 } + %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 } + %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] } + %struct.rtx_def = type { i16, i8, i8, %struct.u } + %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } + %struct.simple_bitmap_def = type { i32, i32, i32, [1 x i64] } + %struct.stack_local_entry = type opaque + %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 } + %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* } + %struct.temp_slot = type opaque + %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* } + %struct.tree_ann_d = type { %struct.stmt_ann_d } + %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 } + %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } + %struct.tree_decl_u1 = type { i64 } + %struct.tree_decl_u2 = type { %struct.function* } + %struct.tree_node = type { %struct.tree_decl } + %struct.u = type { [1 x i64] } + %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* } + %struct.v_may_def_optype_d = type { i32, [1 x %struct.v_def_use_operand_type_t] } + %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } + %struct.varasm_status = type opaque + %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u } + %struct.version_info = type { %struct.tree_node*, %struct.iv*, i1, i32, i1 } + %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] } + +define i1 @determine_use_iv_cost(%struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand) { +entry: + switch i32 0, label %bb91 [ + i32 0, label %bb + i32 1, label %bb6 + i32 3, label %cond_next135 + ] + +bb: ; preds = %entry + ret i1 false + +bb6: ; preds = %entry + br i1 false, label %bb87, label %cond_next27 + +cond_next27: ; preds = %bb6 + br i1 false, label %cond_true30, label %cond_next55 + +cond_true30: ; preds = %cond_next27 + br i1 false, label %cond_next41, label %cond_true35 + +cond_true35: ; preds = %cond_true30 + ret i1 false + +cond_next41: ; preds = %cond_true30 + %tmp44 = call i32 @force_var_cost(%struct.ivopts_data* %data, %struct.tree_node* null, %struct.bitmap_head_def** null) ; <i32> [#uses=1] + %tmp46 = udiv i32 %tmp44, 5 ; <i32> [#uses=1] + call void @set_use_iv_cost(%struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand, i32 %tmp46, %struct.bitmap_head_def* null) + br label %bb87 + +cond_next55: ; preds = %cond_next27 + ret i1 false + +bb87: ; preds = %cond_next41, %bb6 + ret i1 false + +bb91: ; preds = %entry + ret i1 false + +cond_next135: ; preds = %entry + ret i1 false +} + +declare void @set_use_iv_cost(%struct.ivopts_data*, %struct.iv_use*, %struct.iv_cand*, i32, %struct.bitmap_head_def*) + +declare i32 @force_var_cost(%struct.ivopts_data*, %struct.tree_node*, %struct.bitmap_head_def**) diff --git a/test/CodeGen/Blackfin/printf.ll b/test/CodeGen/Blackfin/printf.ll new file mode 100644 index 0000000..d66d1ef --- /dev/null +++ b/test/CodeGen/Blackfin/printf.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +@.str_1 = external constant [42 x i8] ; <[42 x i8]*> [#uses=1] + +declare i32 @printf(i8*, ...) + +define i32 @main(i32 %argc.1, i8** %argv.1) { +entry: + %tmp.16 = call i32 (i8*, ...)* @printf(i8* getelementptr ([42 x i8]* @.str_1, i64 0, i64 0), i32 0, i32 0, i64 0, i64 0) + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/printf2.ll b/test/CodeGen/Blackfin/printf2.ll new file mode 100644 index 0000000..6f402d5 --- /dev/null +++ b/test/CodeGen/Blackfin/printf2.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=bfin +; XFAIL: * +; Assertion failed: (isUsed(Reg) && "Using an undefined register!"), +; function forward, file RegisterScavenging.cpp, line 182. + +declare i32 @printf(i8*, ...) + +define i32 @main() { + %1 = call i32 (i8*, ...)* @printf(i8* undef, i1 undef) + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/promote-logic.ll b/test/CodeGen/Blackfin/promote-logic.ll new file mode 100644 index 0000000..ba2caef --- /dev/null +++ b/test/CodeGen/Blackfin/promote-logic.ll @@ -0,0 +1,42 @@ +; RUN: llvm-as < %s | llc -march=bfin > %t +; XFAIL: * + +; DAG combiner can produce an illegal i16 OR operation after LegalizeOps. + +define void @mng_display_bgr565() { +entry: + br i1 false, label %bb.preheader, label %return + +bb.preheader: + br i1 false, label %cond_true48, label %cond_next80 + +cond_true48: + %tmp = load i8* null + %tmp51 = zext i8 %tmp to i16 + %tmp99 = load i8* null + %tmp54 = bitcast i8 %tmp99 to i8 + %tmp54.upgrd.1 = zext i8 %tmp54 to i32 + %tmp55 = lshr i32 %tmp54.upgrd.1, 3 + %tmp55.upgrd.2 = trunc i32 %tmp55 to i16 + %tmp52 = shl i16 %tmp51, 5 + %tmp56 = and i16 %tmp55.upgrd.2, 28 + %tmp57 = or i16 %tmp56, %tmp52 + %tmp60 = zext i16 %tmp57 to i32 + %tmp62 = xor i32 0, 65535 + %tmp63 = mul i32 %tmp60, %tmp62 + %tmp65 = add i32 0, %tmp63 + %tmp69 = add i32 0, %tmp65 + %tmp70 = lshr i32 %tmp69, 16 + %tmp70.upgrd.3 = trunc i32 %tmp70 to i16 + %tmp75 = lshr i16 %tmp70.upgrd.3, 8 + %tmp75.upgrd.4 = trunc i16 %tmp75 to i8 + %tmp76 = lshr i8 %tmp75.upgrd.4, 5 + store i8 %tmp76, i8* null + ret void + +cond_next80: + ret void + +return: + ret void +} diff --git a/test/CodeGen/Blackfin/promote-setcc.ll b/test/CodeGen/Blackfin/promote-setcc.ll new file mode 100644 index 0000000..b686c54 --- /dev/null +++ b/test/CodeGen/Blackfin/promote-setcc.ll @@ -0,0 +1,40 @@ +; RUN: llvm-as < %s | llc -march=bfin > %t +; XFAIL: * +; Assertion failed: (isUsed(Reg) && "Using an undefined register!"), +; function forward, file RegisterScavenging.cpp, line 259. + +; The DAG combiner may sometimes create illegal i16 SETCC operations when run +; after LegalizeOps. Try to tease out all the optimizations in +; TargetLowering::SimplifySetCC. + +@x = external global i16 +@y = external global i16 + +declare i16 @llvm.ctlz.i16(i16) + +; Case (srl (ctlz x), 5) == const +; Note: ctlz is promoted, so this test does not catch the DAG combiner +define i1 @srl_ctlz_const() { + %x = load i16* @x + %c = call i16 @llvm.ctlz.i16(i16 %x) + %s = lshr i16 %c, 4 + %r = icmp eq i16 %s, 1 + ret i1 %r +} + +; Case (zext x) == const +define i1 @zext_const() { + %x = load i16* @x + %r = icmp ugt i16 %x, 1 + ret i1 %r +} + +; Case (sext x) == const +define i1 @sext_const() { + %x = load i16* @x + %y = add i16 %x, 1 + %x2 = sext i16 %y to i32 + %r = icmp ne i32 %x2, -1 + ret i1 %r +} + diff --git a/test/CodeGen/Blackfin/sdiv.ll b/test/CodeGen/Blackfin/sdiv.ll new file mode 100644 index 0000000..e03f4ff --- /dev/null +++ b/test/CodeGen/Blackfin/sdiv.ll @@ -0,0 +1,5 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs +define i32 @sdiv(i32 %A, i32 %B) { + %R = sdiv i32 %A, %B ; <i32> [#uses=1] + ret i32 %R +} diff --git a/test/CodeGen/Blackfin/simple-select.ll b/test/CodeGen/Blackfin/simple-select.ll new file mode 100644 index 0000000..286db7c --- /dev/null +++ b/test/CodeGen/Blackfin/simple-select.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + +declare i1 @foo() + +define i32 @test(i32* %A, i32* %B) { + %a = load i32* %A + %b = load i32* %B + %cond = call i1 @foo() + %c = select i1 %cond, i32 %a, i32 %b + ret i32 %c +} diff --git a/test/CodeGen/Blackfin/switch.ll b/test/CodeGen/Blackfin/switch.ll new file mode 100644 index 0000000..738fff7 --- /dev/null +++ b/test/CodeGen/Blackfin/switch.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + +define i32 @foo(i32 %A, i32 %B, i32 %C) { +entry: + switch i32 %A, label %out [ + i32 1, label %bb + i32 0, label %bb13 + ] + +bb: ; preds = %entry + ret i32 1 + +bb13: ; preds = %entry + ret i32 1 + +out: ; preds = %entry + ret i32 0 +} diff --git a/test/CodeGen/Blackfin/switch2.ll b/test/CodeGen/Blackfin/switch2.ll new file mode 100644 index 0000000..f0fe1a7 --- /dev/null +++ b/test/CodeGen/Blackfin/switch2.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t + +define i8* @FindChar(i8* %CurPtr) { +entry: + br label %bb + +bb: ; preds = %bb, %entry + %tmp = load i8* null ; <i8> [#uses=1] + switch i8 %tmp, label %bb [ + i8 0, label %bb7 + i8 120, label %bb7 + ] + +bb7: ; preds = %bb, %bb + ret i8* null +} |