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| author | Robert Lytton <robert@xmos.com> | 2013-08-01 08:29:44 +0000 |
|---|---|---|
| committer | Robert Lytton <robert@xmos.com> | 2013-08-01 08:29:44 +0000 |
| commit | dd1cfe21295b9c37a38b7e1f716e76237de10909 (patch) | |
| tree | d98515af015d182b257d38585ffa9b8a86fd36be /test/CodeGen | |
| parent | f2617291e31bc93d3dae2c80d45df5dfb9a70ae5 (diff) | |
| download | external_llvm-dd1cfe21295b9c37a38b7e1f716e76237de10909.zip external_llvm-dd1cfe21295b9c37a38b7e1f716e76237de10909.tar.gz external_llvm-dd1cfe21295b9c37a38b7e1f716e76237de10909.tar.bz2 | |
XCore target: Fix Vararg handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/XCore/2011-08-01-VarargsBug.ll | 17 | ||||
| -rw-r--r-- | test/CodeGen/XCore/varargs.ll | 55 |
2 files changed, 55 insertions, 17 deletions
diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll deleted file mode 100644 index 6445a8f..0000000 --- a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=xcore | FileCheck %s -define void @_Z1fz(...) { -entry: -; CHECK-LABEL: _Z1fz: -; CHECK: extsp 3 -; CHECK: stw r[[REG:[0-3]{1,1}]] -; CHECK: , sp{{\[}}[[REG]]{{\]}} -; CHECK: stw r[[REG:[0-3]{1,1}]] -; CHECK: , sp{{\[}}[[REG]]{{\]}} -; CHECK: stw r[[REG:[0-3]{1,1}]] -; CHECK: , sp{{\[}}[[REG]]{{\]}} -; CHECK: stw r[[REG:[0-3]{1,1}]] -; CHECK: , sp{{\[}}[[REG]]{{\]}} -; CHECK: ldaw sp, sp[3] -; CHECK: retsp 0 - ret void -} diff --git a/test/CodeGen/XCore/varargs.ll b/test/CodeGen/XCore/varargs.ll new file mode 100644 index 0000000..28c2933 --- /dev/null +++ b/test/CodeGen/XCore/varargs.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +define void @_Z1fz(...) { +entry: +; CHECK-LABEL: _Z1fz: +; CHECK: extsp 3 +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: ldaw sp, sp[3] +; CHECK: retsp 0 + ret void +} + + +declare void @llvm.va_start(i8*) nounwind +declare void @llvm.va_end(i8*) nounwind +declare void @f(i32) nounwind +define void @test_vararg(...) nounwind { +entry: +; CHECK-LABEL: test_vararg +; CHECK: extsp 6 +; CHECK: stw lr, sp[1] +; CHECK: stw r0, sp[3] +; CHECK: stw r1, sp[4] +; CHECK: stw r2, sp[5] +; CHECK: stw r3, sp[6] +; CHECK: ldaw r0, sp[3] +; CHECK: stw r0, sp[2] + %list = alloca i8*, align 4 + %list1 = bitcast i8** %list to i8* + call void @llvm.va_start(i8* %list1) + br label %for.cond + +; CHECK-LABEL: .LBB1_1 +; CHECK: ldw r0, sp[2] +; CHECK: add r1, r0, 4 +; CHECK: stw r1, sp[2] +; CHECK: ldw r0, r0[0] +; CHECK: bl f +; CHECK: bu .LBB1_1 +for.cond: + %0 = va_arg i8** %list, i32 + call void @f(i32 %0) + br label %for.cond + + call void @llvm.va_end(i8* %list1) + ret void +} + |